IP Library Granted Patent US 8,049,448
Granted Patent B2
US 8,049,448 · App. 12/465,866 · Granted Nov 1, 2011

Control circuit with dual programmable feedback loops for BLDC motors

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Quick Facts
Patent No.
US 8,049,448
App. No.
12/465,866
Granted
Nov 1, 2011
Kind
B2
Abstract

A BLDC (brushless direct current) motor system of the present invention includes a control circuit, a sequencer, a driving circuit, and a BLDC motor. The control circuit comprises a speed-feedback loop and a torque-feedback loop to control the maximum speed and the maximum torque of the BLDC motor in parallel configuration. The speed-feedback loop generates a speed-control signal. The torque-feedback loop generates a torque-control signal. A PWM circuit receives the speed-control signal and the torque-control signal to generate a PWM signal. A pulse width of the PWM signal is correlated to the level of the speed-control signal and/or the level of the torque-control signal.

Claims (52)

1. A control circuit for controlling a BLDC (brushless direct current) motor, comprising:

a speed synthesizer, coupled to said BLDC motor for generating a speed-feedback signal in response to a plurality of speed-output signals of said BLDC motor;

a torque synthesizer, coupled to said BLDC motor for generating a torque-feedback signal in response to a plurality of switching-current signals, wherein said switching-current signals are correlated to switching currents of said BLDC motor;

a first programmable signal generator, generating a speed-reference signal;

a second programmable signal generator, generating a torque-reference signal;

a first error amplifier, coupled to receive said speed-feedback signal and said speed-reference signal for developing a speed-feedback loop and generating a speed-control signal;

a second error amplifier, coupled to receive said torque-feedback signal and said torque-reference signal for developing a torque-feedback loop and generating a torque-control signal; and

a PWM circuit, generating a PWM signal to drive said BLDC motor in response to said speed-control signal and/or said torque-control signal;

wherein said speed-feedback signal and said torque-feedback signal are analog signals; and

wherein a pulse width of said PWM signal is correlated to the level of said speed-control signal and/or the level of said torque-control signal.

2. The control circuit as claimed in claim 1 , wherein the lower signal among said speed-control signal and said torque-control signal determines said pulse width of said PWM signal.

3. The control circuit as claimed in claim 1 further comprising:

a first compensation capacitor, coupled to an output terminal of said first error amplifier to provide frequency compensation for said speed-feedback loop; and

a second compensation capacitor, coupled to an output terminal of said second error amplifier to provide frequency compensation for said torque-feedback loop.

4. The control circuit as claimed in claim 1 further comprising:

a first filter capacitor, coupled to an output of said speed synthesizer for filtering noise on said speed-feedback signal; and

a second filter capacitor, coupled to an output of said torque synthesizer for filtering noise on said torque-feedback signal.

5. The control circuit as claimed in claim 1 , wherein said first programmable signal generator comprises:

a first current source and a first resistor, generating a first programmable signal; and

a first digital-to-analog converter, generating a first analog signal, wherein said first analog signal is programmed by data provided by an interface;

wherein said speed-reference signal is generated in response to said first programmable signal and said first analog signal.

6. The control circuit as claimed in claim 1 , wherein said second programmable signal generator comprises:

a second current source and a second resistor, generating a second programmable signal; and

a second digital-to-analog converter, generating a second analog signal, wherein said second analog signal is programmed by data provided by an interface;

wherein said torque-reference signal is generated in response to said second programmable signal and said second analog signal.

7. The control circuit as claimed in claim 1 , wherein said speed synthesizer comprises:

a counter, coupled to receive said speed-output signals of said BLDC motor for generating a period signal;

a divider circuit, generating a frequency signal by dividing said period signal with a variable gain, wherein said variable gain is varied in proportion to said period signal; and

a digital-to-analog converter, coupled to receive said frequency signal for generating said speed-feedback signal;

wherein said period signal and said frequency signal are digital signals, and said speed-feedback signal is an analog signal.

8. The control circuit as claimed in claim 1 , wherein said torque synthesizer comprises:

a sampling circuit, coupled to sample said switching-current signals of said BLDC motor for generating a current signal; and

an integration circuit, generating said torque-feedback signal by integrating said current signal; wherein said torque-feedback signal is correlated to said switching currents of said BLDC motor.

9. A method for controlling a BLDC (brushless direct current) motor, comprising:

generating a speed-feedback signal in response to a plurality of speed-output signals of said BLDC motor;

generating a torque-feedback signal in response to a plurality of switching-current signals which are correlated to switching currents of said BLDC motor;

generating a speed-reference signal and a torque-reference signal;

developing a speed-feedback loop to generate a speed-control signal by amplifying an error between said speed-feedback signal and said speed-reference signal;

developing a torque-feedback loop to generate a torque-control signal by amplifying an error between said torque-feedback signal and said torque-reference signal; and

generating a PWM signal to drive said BLDC motor in response to said speed-control signal and/or said torque-control signal;

wherein a pulse width of said PWM signal is correlated to the level of said speed-control signal and/or the level of said torque-control signal.

10. The method as claimed in claim 9 , wherein the lower signal among said speed-control signal and said torque-control signal determines said pulse width of said PWM signal.

11. The method as claimed in claim 9 further comprising:

compensating said speed-feedback loop by connecting a first compensation capacitor to said speed feedback loop; and

compensating said torque-feedback loop by connecting a second compensation capacitor to said torque-feedback loop.

12. The method as claimed in claim 9 , wherein said speed-reference signal is generated by a first current source and a first resistor.

13. The method as claimed in claim 9 , wherein said speed-reference signal is generated by a first digital-to-analog converter.

14. The method as claimed in claim 9 , wherein said torque-reference signal is generated by a second current source and a second resistor.

15. The method as claimed in claim 9 , wherein said torque-reference signal is generated by a second digital-to-analog converter.

16. The method as claimed in claim 9 , wherein said speed-reference signal and said torque-reference signal are generated in response to data provided by an interface.

17. The method as claimed in claim 16 , wherein said interface is a parallel data bus.

18. The method as claimed in claim 16 , wherein said interface is a serial data bus.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RECORDED AT REEL 046410, FRAME 0933 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046410/0933 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2017
From: FAIRCHILD (TAIWAN) CORPORATION (FORMERLY SYSTEM GENERAL CORPORATION)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 042328/0318 →
CHANGE OF NAME Recorded Mar 22, 2017
From: SYSTEM GENERAL CORPORATION
To: FAIRCHILD (TAIWAN) CORPORATION
Reel/Frame 042068/0929 →