Threshold voltage improvement employing fluorine implantation and adjustment oxide layer
View Patent ↗An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type field effect transistors. Fluorine is implanted into the opening to form an epitaxial fluorine-doped semiconductor layer and an underlying fluorine-doped semiconductor layer in the first area. A composite gate stack including a high-k gate dielectric layer and an adjustment oxide layer is formed in the first and second area. P-type and n-type field effect transistors (FET's) are formed in the first and second areas, respectively. The epitaxial fluorine-doped semiconductor layer and the underlying fluorine-doped semiconductor layer compensate for the reduction of the decrease in the threshold voltage in the p-FET by the adjustment oxide portion directly above.
1. A semiconductor structure comprising:
a p-type field effect transistor including a first gate stack and located on a semiconductor substrate, said first gate stack including, from bottom to top, a first high dielectric constant (high-k) gate dielectric having a dielectric constant greater than 4.0, a first adjustment oxide portion, and a first conductive gate material portion, wherein said first high-k gate dielectric abuts a fluorine-doped semiconductor layer;
an n-type field effect transistor including a second gate stack and located on said semiconductor substrate, said second gate stack including, from bottom to top, a second high-k gate dielectric having a dielectric constant greater than 4.0, a second adjustment oxide portion, and a second conductive gate material portion, wherein said second high-k gate dielectric abuts a substantially fluorine-free semiconductor layer; and
another fluorine-doped semiconductor layer located directly beneath said fluorine-doped semiconductor layer and including a different semiconductor material, wherein said another fluorine-doped semiconductor layer and said substantially fluorine-free semiconductor layer have substantially coplanar top surfaces.
2. The semiconductor structure of claim 1 , wherein said first high-k gate dielectric has a same composition and thickness as said second high-k gate dielectric, and wherein said first adjustment oxide portion has a same composition and thickness as said second adjustment oxide portion.
3. The semiconductor structure of claim 2 , wherein said first high-k gate dielectric and said second high-k gate dielectric comprises one of HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaA 1 O x N y , Y 2 O x N y , a silicate thereof, an alloy thereof, and non-stoichiometric variants thereof, wherein each value of x is independently from about 0.5 to about 3 and each value of y is independently from 0 to about 2.
4. The semiconductor structure of claim 2 , wherein said first adjustment oxide portion and said second adjustment oxide portion comprise Be, Mg, Ca, Sr, Ba, Ra, Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, or a combination thereof.
5. The semiconductor structure of claim 1 , wherein said fluorine-doped semiconductor layer has an n-type doping, and wherein said substantially fluorine-free semiconductor layer has a p-type doping.
6. The semiconductor structure of claim 1 , wherein said fluorine-doped semiconductor layer is a fluorine-doped single crystalline silicon-germanium alloy layer, and wherein said another fluorine-doped semiconductor layer is a fluorine-doped single-crystalline silicon layer.
7. The semiconductor structure of claim 6 , wherein said p-type field effect transistor further comprises a first source region and a first drain region, each having a p-type doping and including a portion of said fluorine-doped semiconductor layer and a portion of said another fluorine-doped semiconductor layer, wherein each of said first source region and said first drain region includes a substantially fluorine-free p-doped semiconductor region located beneath said fluorine-doped semiconductor layer.
8. The semiconductor structure of claim 1 , wherein said first high-k gate dielectric is fluorine-doped, and wherein said second high-k gate dielectric is substantially fluorine-free.
9. The semiconductor structure, comprising:
a p-type field effect transistor including a first gate stack and located on a semiconductor substrate, said first gate stack including, from bottom to top, a first high dielectric constant (high- k) gate dielectric having a dielectric constant greater than 4.0, a first adjustment oxide portion, and a first conductive gate material portion, wherein said first high-k gate dielectric abuts a fluorine-doped semiconductor layer;
an n-type field effect transistor including a second gate stack and located on said semiconductor substrate, said second gate stack including, from bottom to top, a second high-k gate dielectric having a dielectric constant greater than 4.0, a second adjustment oxide portion,
and a second conductive gate material portion, wherein said second high-k gate dielectric abuts a substantially fluorine-free semiconductor layer;
another p-type field effect transistor located on said semiconductor substrate, wherein said another p-type field effect transistor includes a third gate stack, said third gate stack including, from bottom to top, a first semiconductor oxide portion, a third high dielectric constant (high-k) gate dielectric having a dielectric constant greater than 4.0, a third adjustment oxide portion, and a third conductive gate material portion, wherein said first semiconductor oxide portion abuts another substantially fluorine-free semiconductor layer; and
another n-type field effect transistor located on said semiconductor substrate, wherein said another n-type field effect transistor includes a fourth gate stack, said fourth gate stack including, from bottom to top, a second semiconductor oxide portion, a fourth high-k gate dielectric having a dielectric constant greater than 4.0, a fourth adjustment oxide portion, and a fourth conductive gate material portion, wherein said second semiconductor oxide portion abuts yet another substantially fluorine-free semiconductor layer.
10. The semiconductor structure of claim 9 , wherein said first high-k gate dielectric has a same composition and thickness as said second high-k gate dielectric, and wherein said first adjustment oxide portion has a same composition and thickness as said second adjustment oxide portion.
11. The semiconductor structure of claim 10 , wherein said first high-k gate dielectric and said second high-k gate dielectric comprises one of HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaA 1 O 3 , Y 2 O 3 , HfO x N y , ZrO x N y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , a silicate thereof, an alloy thereof, and non-stoichiometric variants thereof, wherein each value of x is independently from about 0.5 to about 3 and each value of y is independently from 0 to about 2.
12. The semiconductor structure of claim 10 , wherein said first adjustment oxide portion and said second adjustment oxide portion comprise Be, Mg, Ca, Sr, Ba, Ra, Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, or a combination thereof.
13. The semiconductor structure of claim 9 , wherein said fluorine-doped semiconductor layer has an n-type doping, and wherein said substantially fluorine-free semiconductor layer has a p-type doping.
14. The semiconductor structure of claim 9 , further comprising another fluorine-doped semiconductor layer located directly beneath said fluorine-doped semiconductor layer and including a different semiconductor material, wherein said another fluorine-doped semiconductor layer and said substantially fluorine-free semiconductor layer have substantially coplanar top surfaces.
15. The semiconductor structure of claim 14 , wherein said fluorine-doped semiconductor layer is a fluorine-doped single crystalline silicon-germanium alloy layer, and wherein said another fluorine-doped semiconductor layer is a fluorine-doped single-crystalline silicon layer.
16. The semiconductor structure of claim 15 , wherein said p-type field effect transistor further comprises a first source region and a first drain region, each having a p-type doping and including a portion of said fluorine-doped semiconductor layer and a portion of said another fluorine-doped semiconductor layer, wherein each of said first source region and said first drain region includes a substantially fluorine-free p-doped semiconductor region located beneath said fluorine-doped semiconductor layer.
17. The semiconductor structure of claim 9 , wherein said first high-k gate dielectric is fluorine-doped, and wherein said second high-k gate dielectric is substantially fluorine-free.