Cache coherent support for flash in a memory hierarchy

1. A computer system, comprising:

a processor coupled to a memory hierarchy via a memory controller;

wherein the memory hierarchy includes a first memory region comprising random access memory and an auxiliary memory region comprising flash memory;

wherein the memory controller is coupled to the auxiliary memory region via a flash controller;

wherein in response to detecting a page fault, the processor is configured to swap a page from the auxiliary memory region to the first memory region:

wherein a command sequencer within the processor executes a sequence of micro commands stored in the first memory region to move said data between the auxiliary memory region and the first memory region.

2. The computer system of claim 1 , wherein the first memory region, the auxiliary memory region, and the flash controller comprise a dual-in-line module.

3. The computer system of claim 1 , wherein the processor includes at least two processors that share the first memory region and the auxiliary memory region.

4. A computer system, comprising:

a processor coupled to a memory hierarchy via a memory controller and at least one cache memory;

wherein the memory hierarchy includes a first memory region comprising random access memory and an auxiliary memory region comprising flash memory;

wherein the memory controller is coupled to the auxiliary memory region via a flash controller;

wherein in response to detecting a page fault, the processor is configured to swap a page from the auxiliary memory region to the first memory region;

wherein the processor further comprises a coherence engine configured to:

detect a page fault corresponding to a request, and

in response to detecting the page fault, invalidate one or more cache lines in the at least one cache memory that correspond to the particular page; and

flush the one or more cache lines.

5. The computer system of claim 4 , wherein prior to said move, the coherence engine is configured to flush the one or more cache lines.

6. A computer system, comprising:

a processor coupled to a memory hierarchy via a memory controller and at least one cache memory;

wherein the memory hierarchy includes a first memory region comprising random access memory and an auxiliary memory region comprising flash memory;

wherein the memory controller is coupled to the auxiliary memory region via a flash controller;

wherein in response to detecting a page fault, the processor is configured to swap a page from the auxiliary memory region to the first memory region;

wherein the first memory region and the auxiliary memory region are interconnected through a cache buffer;

wherein to move data from the first memory region to the auxiliary memory region, the processor is configured to:

read data from the first memory region to the cache buffer; and

write data from the cache buffer to the auxiliary memory region; and

wherein to move data from the auxiliary memory region to the first memory region, the processor is configured to:

read data from the auxiliary memory region to the cache buffer; and

write data from the cache buffer to the first memory region.

7. A method, comprising:

receiving a request from a processor to access a particular page in a first memory region of a memory hierarchy, the first memory region comprising random access memory;

detecting a page fault corresponding to the request, and

in response to detecting the page fault, swapping a page to the first memory region from an auxiliary memory region of the memory hierarchy, the auxiliary region comprising flash memory;

wherein swapping a page further comprises a command sequencer within the processor moving data between the auxiliary memory region and the first memory region, wherein moving data between the auxiliary memory region and the first memory region comprises executing a sequence of micro commands that are stored in the first memory region.

8. The method of claim 7 , wherein the first memory region, the auxiliary memory region, and the flash controller comprise a dual-in-line module.

9. The method of claim 7 , further comprising sharing the first memory region and the auxiliary memory region with at least two processors.

10. A method, comprising:

receiving a request from a processor to access a particular page in a first memory region of a memory hierarchy, the first memory region comprising random access memory;

detecting a page fault corresponding to the request, and

in response to detecting the page fault, swapping a page to the first memory region from an auxiliary memory region of the memory hierarchy, the auxiliary region comprising flash memory;

wherein the processor includes at least one cache memory and the method in response to detecting the page fault, includes invalidating one or more cache lines in the at least one cache memory that correspond to the particular page; and flushing the one or more cache lines.

11. The method of claim 10 , wherein the one or more cache lines are flushed prior to moving data between the auxiliary memory region and the first memory region.

12. A method, comprising:

receiving a request from a processor to access a particular page in a first memory region of a memory hierarchy, the first memory region comprising random access memory;

detecting a page fault corresponding to the request, and

in response to detecting the page fault, swapping a page to the first memory region from an auxiliary memory region of the memory hierarchy, the auxiliary region comprising flash memory;

wherein the first memory region and the auxiliary memory region are interconnected through a cache buffer;

wherein moving data from the first memory region to the auxiliary memory region further comprises:

reading data from the first memory region to the cache buffer; and

writing data from the cache buffer to the auxiliary memory region; and

wherein moving data from the auxiliary memory region to the first memory region further comprises:

reading data from the auxiliary memory region to the cache buffer; and

writing data from the cache buffer to the first memory region.

13. A computer-readable storage medium containing instructions that, when executed, enable a memory controller to:

receive a request from a processor to access a particular page in a first memory region of a memory hierarchy, the first memory region comprising random access memory;

detect a page fault corresponding to the request;

in response to detecting the page fault, swap a page to the first memory region from an auxiliary memory region of the memory hierarchy, the auxiliary region comprising flash memory; and

cause a command sequencer within the processor to execute a sequence of micro commands stored in the first memory region to swap the page.

14. A computer-readable storage medium containing instructions that, when executed, enable a memory controller to:

receive a request from a processor to access a particular page in a first memory region of a memory hierarchy, the first memory region comprising random access memory;

detect a page fault corresponding to the request; and

in response to detecting the page fault, swap a page to the first memory region from an auxiliary memory region of the memory hierarchy, the auxiliary region comprising flash memory;

wherein the processor includes at least one cache memory and the instructions are further executable by a coherence engine within the processor to:

detect a page fault corresponding to the request;

in response to detecting the page fault, invalidate one or more cache lines in the at least one cache memory that correspond to the particular page; and

flush the one or more cache lines.

15. A computer-readable storage medium containing instructions that, when executed, enable a memory controller to:

receive a request from a processor to access a particular page in a first memory region of a memory hierarchy, the first memory region comprising random access memory;

detect a page fault corresponding to the request; and

in response to detecting the page fault, swap a page to the first memory region from an auxiliary memory region of the memory hierarchy, the auxiliary region comprising flash memory;

wherein the first memory region and the auxiliary memory region are interconnected through a cache buffer;

wherein moving data from the first memory region to the auxiliary memory region further comprises:

reading data from the first memory region to the cache buffer; and

writing data from the cache buffer to the auxiliary memory region; and

wherein moving data from the auxiliary memory region to the first memory region further comprises:

reading data from the auxiliary memory region to the cache buffer; and

writing data from the cache buffer to the first memory region.