Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films
View Patent ↗A thin film transistor (TFT) array panel that includes a substrate, a gate wire including a gate pad, a gate insulating layer pattern, a semiconductor layer pattern, an ohmic contact layer pattern, a data wire including a data pad and a drain electrode, and a passivation layer pattern is presented. The passivation layer pattern is formed on the data wire and has contact holes exposing the gate pad, the data pad, and the drain electrode. The passivation layer pattern also has a planar shape that is similar that of the semiconductor layer pattern due to simultaneous etching except for the portions adjoining the drain electrode and the data pad, having a width greater than that of the data wire, and covering a boundary line of the data wire. A pixel electrode is electrically connected to the exposed portion of the drain electrode and contacts the gate insulating layer pattern.
1. A thin film transistor (TFT) array panel, comprising:
a substrate;
a gate wire formed on the substrate and including a gate line, a gate electrode and a gate pad;
a gate insulating layer pattern formed on the gate wire;
a semiconductor layer pattern formed on the gate insulating layer pattern;
an ohmic contact layer pattern formed on the semiconductor layer pattern;
a data wire formed on the ohmic contact layer pattern, including a data line, a source electrode, a drain electrode and a data pad, and having a planar shape substantially the same as that of the ohmic contact layer pattern due to simultaneous etching;
a passivation layer pattern formed on the data wire, having contact holes exposing the gate pad, the data pad and the drain electrode, having a planar shape substantially the same as that of the semiconductor layer pattern due to simultaneous etching except for the portions adjoining the drain electrode and the data pad, having a width greater than that of the data wire, and covering a boundary line of the data wire; and
a pixel electrode electrically connected to the exposed portion of the drain electrode,
wherein a portion of the pixel electrode is in direct contact with an upper surface of the gate insulating layer pattern.
2. The TFT array panel of claim 1 , further comprising a storage electrode formed over the gate line,
wherein the semiconductor layer pattern and the ohmic contact layer pattern have a portion interposed between the storage electrode and the gate line, and the storage electrode is connected to the pixel electrode.
3. The TFT array panel of claim 1 , wherein the passivation layer pattern has a boundary line substantially the same as that off the semiconductor layer pattern except for portions adjoining the drain electrode and the data pad, having a width greater than that of the data wire, and covering a boundary line of the data wire.
4. The TFT array panel of claim 1 , wherein the gate insulating layer pattern has a shape different from that of the passivation layer pattern under the pixel electrode.
5. The TFT array panel of claim 1 , further comprising a redundant gate pad and a redundant data pad covering the gate pad and the data pad, respectively.