Method and apparatus for packaging circuit devices
View Patent ↗A hermetically sealed package includes a lid ( 14 ) hermetically bonded to a wafer or substrate ( 12 ), with a chamber therebetween defined by a recess ( 16 ) in the lid. A circuit device ( 26 ) such as MEMS device is provided within the chamber on the substrate. A plurality of vias ( 41 - 46 ) are provided through the substrate, and each have a structure which facilitates a hermetic seal of a suitable level between opposite sides of the substrate. The vias provide electrical communication from externally of the assembly to the device disposed in the chamber.
1. A method comprising:
providing a wafer comprisng:
a first side;
a second side;
a plurality of sections disposed on the first side; and
a plurality of first annular surface portions disposed on a respective one of the plurality of sections;
forming a plurality of spaced structures on the first side of the wafer in a manner so that each of the structures is on a respective one of the sections, and so that each of the first annular surface portions extends around a respective one of the spaced structures;
providing a cover, the cover having on one side thereof a plurality of second annular surface portions which are each engageable with a respective one of the first annular surface portions;
bonding each of the first annular surface portions to a respective one of the second annular surface portions to create a plurality of hermetically sealed chambers between the wafer and the cover, each hermetically sealed chamber having therein a respective one of the structures;
creating an opening through the wafer that extends from the first side to the second side; and
forming a via within the opening, the via operable to provide a hermetic seal within the opening with respect to the first and second sides of the wafer, the via comprising:
a first end adjacent to the first side of the wafer;
a second end adjacent to the second side of the wafer;
a conductive portion operable to provide electrical conductivity between the first end and the second end;
forming a sleevelike portion with an electrically conductive material within the via; and
forming an electrically non-conductive core portion within the sleevelike portion.
2. The method of claim 1 , wherein forming the plurality of spaced structures comprises electrically coupling one of the spaced structure to the first end of the conductive portion of the via.
3. The method of claim 1 , further comprising cutting the wafer and cover into a plurality of portions, each portion comprising:
a respective one of the sections of the wafer;
a respective one of the structures;
a respective one of the first annular surface portions; and
a respective one of the second annular surface portions.
4. The method of claim 1 , wherein forming the sleevelike portion comprises:
forming an outer sleeve comprising titanium tungsten; and
thereafter forming within the outer sleeve an inner sleeve comprising gold.
5. The method of claim 1 , wherein the non-conductive core portion comprises a glass material.
6. The method of claim 1 , further comprising forming on the second side of the wafer a conductive ground layer having an opening therethrough with a size greater than a size of the second end of the via, the second end of the via being positioned within the opening through the ground layer in a manner so that the conductive portion of the via is free of contact with the ground layer.
7. The method of claim 1 , wherein the cover comprises a glass material.
8. The method of claim 1 , wherein providing the cover comprises forming a plurality of recesses in a side of the cover facing the substrate, the plurality of recesses forming a respective one of the chambers, each of the second annular surface portions extending around one of the respective recesses.
9. The method of claim 1 , wherein the plurality of spaced structures comprises a plurality of micro-electro-mechanical systems.