Digital demodulating apparatus for timing error detection

1. A digital demodulating apparatus, comprising:

a numerically controlled oscillator (NCO) generating a first sequence signal according to an input sequence signal and a timing error sequence signal;

an equalizer unit equalizing the first sequence signal to generate an equalized sequence signal;

a decoder decoding the equalized sequence signal to generate an output sequence signal;

a timing error detector generating the timing error sequence signal according to the first sequence signal and one of the equalized sequence signal and the output sequence signal; and

a buffer buffering the first sequence signal so as to generate a compensated first sequence signal, wherein the timing error detector generates the timing error sequence signal according to the compensated first sequence signal and one of the equalized sequence signal and the output sequence signal,

wherein the timing error detector generates the timing error sequence signal further according to a previous compensated first sequence signal and one of a previous output sequence signal and a previous equalized sequence signal, and

wherein the timing error sequence signal is generated according to the following formula:

e ( n )= a ( n −1) y ( n )− a ( n ) y ( n −1),

 wherein e(n) is the timing error sequence signal, a(n) is the output sequence signal, a(n−1) is the previous output sequence signal prior to a(n), y(n) is the compensated first sequence signal, and y(n−1) is the previous compensated first sequence signal prior to y(n).

2. The digital demodulating apparatus as claimed in claim 1 , wherein the decoder is a Viterbi decoder.

3. A digital demodulating apparatus, comprising:

a numerically controlled oscillator (NCO) generating a first sequence signal according to an input sequence signal and a timing error sequence signal;

an equalizer unit, comprising:

an equalizer equalizing the first sequence signal to generate an equalized sequence signal according to a sliced sequence signal; and

a slicer slicing the equalized sequence signal to generate the sliced sequence signal according to a reference signal;

a decoder decoding the equalized sequence signal to generate an output sequence signal and the reference signal during the decoding phase of the equalized sequence signal;

a timing error detector generating the timing error sequence signal according to the first sequence signal and one of the sliced sequence signal, the equalized sequence signal and the output sequence signal; and

a buffer buffering the first sequence signal so as to generate a compensated first sequence signal, wherein the timing error detector generates the timing error sequence signal according to the compensated first sequence signal and one of the sliced sequence signal, the equalized sequence signal and the output sequence signal,

wherein the timing error detector generates the timing error sequence signal further according to a previous compensated first sequence signal and one of a previous sliced sequence signal, a previous equalized sequence signal and a previous output sequence signal, and

wherein the timing error sequence signal is generated according to the following formula:

e ′( n )= a ′( n −1) y ( n )− a ′( n ) y ( n −1),

 wherein e′(n) is the timing error sequence signal, a′(n) is the sliced sequence signal, a′(n−1) is the previous sliced sequence signal prior to a′(n), y(n) is the compensated first sequence signal, and y(n−1) is the previous compensated first sequence signal prior to y(n).

4. The digital demodulating apparatus as claimed in claim 3 , wherein the decoder is a Viterbi decoder.

5. The digital demodulating apparatus as claimed in claim 3 , wherein the reference signal includes path metric and trellis-coded modulation information.

6. The digital demodulating apparatus as claimed in claim 3 , wherein the slicer further changes its decision boundary according to the reference signal.