Transversal filter circuit with a plurality of delay units, multiplexers, and full adders suited for a smaller decision feedback equalizer
View Patent ↗A transversal filter circuit comprises a plurality of delay units, a plurality of multiplexers and a plurality of full adders. The plurality of delay units is coupled in series to delay a two-bit input signal. The plurality of multiplexers is coupled to the plurality of delay units in a one-to-one manner, and outputs zero, a data signal, or the inverse of the data signal according to the output signals of the plurality of delay units. The plurality of full adders accumulates the outputs of the plurality of multiplexers and the MSB of the outputs of the plurality of the delay units.
1. A transversal filter, comprising:
a plurality of serially coupled delay units configured to delay a two-bit input signal;
a plurality of multiplexers, each of the multiplexer having a control input terminal coupled to an output terminal of one of the delay units, and having data input terminals separately coupled to zero, a data signal and an inverse of the data signal; and
a plurality of full adders coupled in a tree structure, each of the full adders having a numeral input terminal coupled to an output terminal of a full adder at an upper layer or an output terminal of one of the multiplexers, and having a carry-in input terminal coupled to a most significant bit of the output terminal of one of the delay units.
2. The transversal filter of claim 1 , wherein when the control input of one of the multiplexers is 2′b01, the multiplexer outputs the data signal.
3. The transversal filter of claim 1 , wherein when the control input of one of the multiplexers is 2′b10, the multiplexer outputs the inverse of the data signal.
4. The transversal filter of claim 1 , wherein when the control input of one of the multiplexers is 2′b00, the multiplexer outputs zero.
5. The transversal filter of claim 1 , wherein the quantity of delay units is equal to the quantity of multiplexers.
6. The transversal filter of claim 1 , wherein the quantity of multiplexers is equal to the quantity of full adders.
7. The transversal filter of claim 1 , wherein the two-bit input signal is represented in multi-level transmit with 3 voltage levels representation.
8. The transversal filter of claim 1 , wherein the delay units are registers.
9. The transversal filter of claim 1 , further comprising:
a plurality of inverters, each of the inverters configured to provide one of multiplexers with the inverse of the data signal, wherein an input terminal of each of the inverters is coupled to the data signal, and an output terminal of each of the inverters is coupled to one of multiplexers.
10. The transversal filter of claim 1 , which is applied in a decision feedback equalization system.
11. A transversal filter, comprising:
a plurality of serially coupled delay units configured to delay a two-bit input signal;
a plurality of multiplexers, each of the multiplexer configured to output zero, a data signal or an inverse of the data signal according to an output signal of one of the delay units, wherein the inverse of the data signal is not generated by an adder; and
a plurality of full adders, each of the full adders configured to accumulate an output signal of one of the multiplexers and the most significant bit of the output signal of one of the delay units.
12. The transversal filter of claim 11 , wherein when the output signals of one of the delay units is 1, the corresponding multiplexer outputs the data signal.
13. The transversal filter of claim 11 , wherein when the output signal of one of the delay units is −1, the corresponding multiplexer outputs the inverse of the data signal.
14. The transversal filter of claim 11 , wherein when the output signal of one of the delay units is 0, the corresponding multiplexer outputs zero.
15. The transversal filter of claim 11 , wherein the quantity of delay units is equal to the quantity of multiplexers.
16. The transversal filter of claim 11 , wherein the quantity of multiplexers is equal to the quantity of full adders.
17. The transversal filter of claim 11 , wherein the two-bit input signal is represented in multi-level transmit with 3 voltage levels representation.
18. The transversal filter of claim 11 , wherein the delay units are registers.
19. The transversal filter of claim 11 , further comprising:
a plurality of inverters, each of the inverters configured to provide one of multiplexers with the inverse of the data signal, wherein an input terminal of each of the inverters is coupled to the data signal, and an output terminal of each of the inverters is coupled to one of multiplexers.
20. The transversal filter of claim 11 , which is applied in a decision feedback equalization system.