INTEGRATED CIRCUIT SYSTEM WITH VERTICAL CONTROL GATE AND METHOD OF MANUFACTURE THEREOF

1 . A method of manufacture of an integrated circuit system comprising:

providing a mesa over a substrate;

forming a trench in the substrate adjacent the mesa;

forming a second gate and a charge storage material along a trench sidewall; and

forming a first gate from the mesa.

2 . The method as claimed in claim 1 wherein:

providing the mesa includes providing a select gate dielectric layer, a select gate layer and a cap layer.

3 . The method as claimed in claim 1 wherein:

forming the trench in the substrate includes a self aligned process.

4 . The method as claimed in claim 1 wherein:

forming the charge storage material includes forming silicon nanocrystals or metal nanoclusters.

5 . The method as claimed in claim 1 wherein:

forming the first gate from the mesa includes etching a group of layers deposited before forming the trench.

6 . A method of manufacture of an integrated circuit system comprising:

providing a first gate layer formed over a substrate;

forming a trench in the substrate aligned to the first gate layer;

forming a charge storage material within the trench and over the first gate layer;

forming a second gate layer over the charge storage material within the trench and over the first gate layer;

forming a second gate and a second gate dielectric along a trench sidewall from the second gate layer and the charge storage material; and

forming a first gate from the first gate layer.

7 . The method as claimed in claim 6 wherein:

forming the first gate includes forming a select gate.

8 . The method as claimed in claim 6 wherein:

forming the second gate includes forming a control gate.

9 . The method as claimed in claim 6 wherein:

forming the second gate dielectric includes forming a control gate bottom dielectric layer, a charge storage material, and a control gate top dielectric layer;

10 . The method as claimed in claim 6 wherein:

forming the trench affects the desired gate length of a control gate.

11 . A method of manufacture of an integrated circuit system comprising:

providing a mesa including a first gate dielectric, a first gate layer, and a cap layer over a substrate;

forming a trench in the substrate aligned to the mesa;

forming a charge storage material within the trench and over the mesa;

forming a second gate layer over the charge storage material within the trench and over the mesa;

forming a second gate and a second gate dielectric along a trench sidewall from the second gate layer and the charge storage material;

forming a first gate from the mesa; and

forming a doped region adjacent the first gate and the second gate.

12 . The system as claimed in claim 11 wherein:

forming the first gate includes forming a select gate.

13 . The system as claimed in claim 11 wherein:

forming the second gate includes forming a control gate.

14 . The system as claimed in claim 11 wherein:

forming the charge storage material includes forming silicon nanocrystals or metal nanoclusters.

15 . The system as claimed in claim 11 wherein:

forming the first gate from the mesa includes etching a group of layers deposited before forming the trench.

16 . The system as claimed in claim 11 wherein:

forming the second gate dielectric includes forming a control gate bottom dielectric layer, a charge storage material, and a control gate top dielectric layer.

17 . The system as claimed in claim 16 wherein:

forming the trench affects the desired gate length of a control gate

18 . The system as claimed in claim 16 wherein:

forming the second gate includes forming a control gate along a mesa sidewall, the trench sidewall and a portion of a trench bottom.

19 . The system as claimed in claim 16 wherein:

forming the second gate includes a self-aligned process.

20 . The system as claimed in claim 16 further comprising:

configuring the integrated circuit system to include a nonvolatile memory.