Data processing device
View Patent ↗A data processing device has an instruction decoder ( 1 ), a control logic unit ( 3 ), and ALU ( 4 ). The instruction decoder ( 1 ) decodes instruction codes of an arithmetic instruction. The control logic unit ( 3 ) detects the effective data width of operation data to be processed according to the decode result from the instruction decoder ( 1 ) and determines the number of cycles for the instruction execution corresponding to the effective data width. The ALU ( 4 ) executes the instruction with the number of cycles of the instruction execution determined by the control logic unit ( 3 ).
1. A data processor comprising:
a divider for executing a divide calculation based on a divide instruction; and
a data size determining unit for determining data sizes of a dividend and a divisor instructed in the divide instruction during an execution of the divide instruction,
wherein a calculation cycle count of the divide calculation executed by the divider is determined depending on the data sizes of the dividend and the divisor.
2. A data processor according to claim 1 ,
wherein the divide instruction contains information indicating whether each of the dividend and the divisor is the signed form number or the unsigned form number, and
wherein the data size determining unit determines the data sizes of the dividend and the divisor based on the information in the divide instruction.
3. A data processor according to claim 2 , further comprising a plurality of registers,
wherein the dividend and the divisor are stored in registers instructed by the divide instruction.
4. A data processor having a divide calculation function in response to fetching a divide instruction, a data size determining function for determining data sizes of a dividend and a divisor during an execution of the divide instruction, and a calculation cycle number determining function determining a calculation cycle number of the divide calculation function depending on the data sizes of the dividend and the divisor.