Scalable non-blocking switching network for programmable logic
View Patent ↗A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.
1. An integrated circuit, comprising a L-level permutable switching network (L-PSN);
wherein the L-PSN comprises:
(L+2) levels of conductors,
wherein each of the (L+2) levels of conductors comprises I i number of conductors for i=[0:L+1],
wherein the i-th level of conductors of I i number of conductors comprises Π q=[0:i] D[q] sets of conductors where each of the Π q=[0:i] D[q] sets of conductors comprises (I i /Π q=[0:i] D[q]) number of conductors for i=[0:L+1] where D[0]=1 and D[i]≧1,
wherein at least one D[i] is at least three for an i selected from [1:L+1], wherein the I i−1 number of conductors of the (i−1)-th level of conductors selectively couple to the I i−1 number of conductors of the i-th level of conductors through at least T=(I i−1 −D[i]+1)×D[i] number of switches without requiring traversal of any other conductors for i=[1:L+1];
at least one j selected from [1:L+1],
wherein at least one of the Π q=[0:j−1] D[q] sets of conductors comprising (I j−1 /Π q=[0:j−1] D[q]) number of conductors comprises (I j /Π q=[0:j] D[q]) groups of ((I j−1 /I j )×D[j]) number of conductors of the (j−1)-th level of conductors, and
wherein each of the (I j /Π q=[0:j] D[q]) groups of the ((I j−1 /I j )×D[j]) number of conductors of the (j−1)-th level of conductors selectively couple to one conductor in each of the D[j] sets of conductors comprising (I j /Π q=[0:j] D[q]) number of conductors of the j-th level of conductors through a respective ((I j−1 /I j )×D[j]) number of switches without requiring traversal of another conductor.
2. The integrated circuit of claim 1 , wherein each one of the Π q=[0:j−1] D[q] sets of conductors of (I j−1 /Π q=[0:j−1] D[q]) number of conductors comprises (I j /Π q=[0:j] D[q]) groups of ((I j−1 /I j )×D[j]) number of conductors of the (j−1)-th level of conductors, and
wherein each of the (I j /Π q=[0:j] D[q]) groups of the ((I j−1 /I j )×D[j]) number of conductors selectively couple to one conductor in each of the D[j] sets of conductors of the (I j /Π q=[0:j] D[q]) number of conductors of the j-th level of conductors through a respective ((I j−1 /I j )×D[j]) number of switches without requiring traversal of another conductor.
3. The integrated circuit of claim 1 , wherein T=(I i−1 ×D[i]).
4. The integrated circuit of claim 1 , wherein I j ≧I j−1 .
5. A method to manufacture an integrated circuit, comprising:
fabricating a L-level permutable switching network (L-PSN),
wherein the L-PSN comprises:
(L+2) levels of conductors,
wherein each of the (L+2) levels of conductors comprises I i number of conductors for i=[0:L+1],
wherein the i-th level of conductors of I i number of conductors comprises Π q=[0:i] D[q] sets of conductors where each of the Π q=[0:i] D[q] sets of conductors comprises (I i /Π q=[0:i] D[q]) number of conductors for i=[0:L+1] where D[0]=1 and D[i]≧1,
wherein at least one D[i] is at least three for an i selected from [1:L+1],
wherein the I i−1 number of conductors of the (i−1)-th level of conductors selectively couple to the I i−1 number of conductors of the i-th level of conductors through at least T=(I i−1 −D[i]+1)×D[i] number of switches without requiring traversal of any other conductors for i=[ 1 :L+1];
at least one j selected from [1:L+1],
wherein at least one of the Π q=[0:j−1] D[q] sets of conductors comprising (I j−1 /Π q=[0:j−1] D[q]) number of conductors comprises (I j /Π q=[0:j] D[q]) groups of ((I j−1 /I j )×D[j]) number of conductors of the (j−1)-th level of conductors, and
wherein each of the (I j /Π q=[0:j] D[q]) groups of the ((I j−1 /I j )×D[j]) number of conductors of the (j−1)-th level of conductors selectively couple to one conductor in each of the D[j] sets of conductors comprising (I j−1 /Π q=[0:j] D[q]) number of conductors of the j-th level of conductors through a respective ((I j−1 /I j )×D[j]) number of switches without requiring traversal of another conductor.
6. The method of claim 5 , wherein T=(I i−1 ×D[i]).
7. The method of claim 5 , wherein each one of the Π q=[0:j−1] D[q] sets of conductors of (I j−1 /Π q=[0:j−1] D[q]) number of conductors comprises (I j /Π q=[0:j] D[q]) groups of ((I j−1 /I j )×D[j]) number of conductors of the (j−1)-th level of conductors, and
wherein each of the (I j /Π q=[0:j] D[q]) groups of the ((I j−1 /I j )×D[j]) number of conductors selectively couple to one conductor in each of the D[j] sets of conductors of the (I j /Π q=[0:j] D[q]) number of conductors of the j-th level of conductors through a respective ((I j−1 /I j )×D[j]) number of switches without requiring traversal of another conductor.
8. The method of claim 5 , wherein I j ≧I j−1 .
9. An article of manufacture comprising a machine readable storage medium that stores data representing an integrated circuit layout, comprising: a L-level permutable switching network (L-PSN);
wherein the L-PSN comprises:
(L+2) levels of conductors,
wherein each of the (L+2) levels of conductors comprises I i number of conductors for i=[0:L+1],
wherein the i-th level of conductors of I i number of conductors comprises Π q=[0:i] D[q] sets of conductors where each of the Π q=[0:i] D[q] sets of conductors comprises (I i /Π q=[0:i] D[q]) number of conductors for i=[0:L+1] where D[0]=1 and D[i]≧1,
wherein at least one D[i] is at least three for an i selected from [1:L+1],
wherein the I i−1 number of conductors of the (i−1)-th level of conductors selectively couple to the I i number of conductors of the i-th level of conductors through at least T=(I i−1 −D[i]+1)×D[i] number of switches without requiring traversal of any other conductors for i=[1:L+1];
at least one j selected from [1:L+1],
wherein at least one of the Π q=[0:j−1] D[q] sets of conductors comprising (I j−1 /Π q=[0:j−1] D[q]) number of conductors comprises (I j−1 /Π q=[0:j] D[q]) groups of ((I j−1 /I j )×D[j]) number of conductors of the (j−1)-th level of conductors, and
wherein each of the (I j /Π q=[0:j] D[q]) groups of the ((I j−1 /I j )×D[j]) number of conductors of the (j−1)-th level of conductors selectively couple to one conductor in each of the D[j] sets of conductors comprising (I j /Π q=[0:j] D[q]) number of conductors of the j-th level of conductors through a respective ((I j−1 /I j )×D[j]) number of switches without requiring traversal of another conductor.
10. The article of manufacture of claim 9 , wherein T=(I i−1 ×D[i]).
11. The article of manufacture of claim 9 , wherein each one of the Π q=[0:j−1] D[q] sets of conductors of (I j−1 /Π q=[0:j−1] D[q]) number of conductors comprises (I j /Π q=[0:j] D[q]) groups of ((I j−1 /I j )×D[j]) number of conductors of the (j−1)-th level of conductors, and
wherein each of the (I j /Π q=[0:j] D[q]) groups of the ((I j−1 /I j )×D[j]) number of conductors selectively couple to one conductor in each of the D[j] sets of conductors of the (I j /Π q=[0:j] D[q]) number of conductors of the j-th level of conductors through a respective ((I j−1 /I j )×D[j]) number of switches without requiring traversal of another conductor.
12. The article of manufacture of claim 9 , wherein I j ≧I j−1 .