Amplifier with bypass switch
View Patent ↗An amplifying circuit of a receiver for receiving a signal in a wireless network includes an amplifier and a switch. The amplifier includes an amplifying transistor having a gate connected to an input for receiving the signal and a source/drain connected to a voltage source through an inductance. The amplifier also includes a bypass transistor having a gate connected to a control signal for activating the bypass transistor in a bypass mode and a source/drain connected in parallel with the inductance. The switch is connected in parallel with the amplifier between the input and an output, and activates in the bypass mode, enabling the received signal to bypass the amplifier. In the bypass mode, a voltage at the source/drain of the amplifying transistor is lower when the bypass transistor is activated than when not activated, the lower source/drain RF voltage reducing unwanted harmonics from the amplifier.
1. An amplifier circuit of a receiver for receiving a signal in a wireless network, the amplifying circuit comprising:
an amplifier comprising an amplifying transistor and a bypass transistor, the amplifying transistor having a gate connected to an input for receiving the signal and a source/drain connected to a voltage source through an inductance, and the bypass transistor having a gate connected to a control signal for activating the bypass transistor in a bypass mode and a source/drain connected between the voltage source and the source/drain of the amplifying transistor in parallel with the inductance; and
a switch connected in parallel with the amplifier between the input and an output, the switch being configured to activate in the bypass mode, enabling the received signal to bypass the amplifier,
wherein, in the bypass mode, a voltage at the source/drain of the amplifying transistor is lower when the bypass transistor is activated than when the bypass transistor is not activated, the lower source/drain RF voltage reducing unwanted harmonics from the amplifier.
2. The amplifier circuit of claim 1 , wherein, when activated, the switch provides an insertion loss that attenuates signal strength of the received signal passing through the switch in the bypass mode.
3. The amplifier circuit of claim 2 , wherein each of the amplifying transistor, the bypass transistor and the switch comprises a field effect transistor.
4. The amplifier circuit of claim 1 , wherein, when activated, the bypass transistor shifts a resonance of the received signal toward a lower frequency.
5. The amplifier circuit of claim 1 , wherein, when activated, the bypass transistor causes a high reflection load at the gate of the amplifying transistor, reducing an amount of power of the received signal passing through the amplifier in the bypass mode.
6. The amplifier circuit of claim 1 , further comprising:
a processor configured to compare signal strength of the received signal to a threshold, and to generate the control signal to activate the bypass transistor and the switch when the signal strength of the received signal exceeds the threshold.
7. A radio frequency (RF) amplifying circuit comprising:
an amplifier connected between a signal input and a signal output, the amplifier being configured to amplify an RF signal received through the signal input and to output the amplified RF signal through the signal output in an amplify mode; and
a switch connected in parallel with the amplifier between the signal input and the signal output, the switch being configured to deactivate in the amplify mode and to activate in a bypass mode, and being further configured to attenuate the RF signal received through the signal input in the bypass mode,
wherein the amplifier comprises:
a first amplifying transistor having a first gate connected to the signal input, a first source connected to a ground voltage, and a first drain connected to a voltage source through an inductor, the inductor having an inductor impedance; and
a variable impedance circuit connected between the first drain and the voltage source in parallel with the inductor, the variable impedance circuit having a first impedance greater than the inductor impedance in the amplify mode and has a second impedance less than the inductor impedance in the bypass mode.
8. The amplifying circuit of claim 7 , wherein the variable impedance circuit comprises a bypass transistor, a first capacitor and a second capacitor connected in series between the first drain and the voltage source.
9. The amplifying circuit of claim 8 , wherein the bypass transistor is turned on in the bypass mode and turned off in the amplify mode.
10. The amplifying circuit of claim 9 , further comprising:
a first bias circuit for biasing the first amplifying transistor in the amplify mode.
11. The amplifying circuit of claim 10 , wherein the first circuit is activated by a control signal and the bypass transistor is deactivated by an inverse of the control signal in the amplify mode.
12. The amplifying circuit of claim 10 , wherein the first bias circuit is deactivated by a control signal and the bypass transistor is activated by an inverse of the control signal in the bypass mode.
13. The amplifying circuit of claim 10 , further comprising:
a second amplifying transistor having a second gate connected to the first drain, a second source connected to the ground voltage, and a second drain connected to the signal output; and
a second bias circuit for biasing the second amplifying transistor in the amplify mode.
14. An amplifying circuit of a receiver for receiving a radio frequency (RF) signal through a signal input, the amplifying circuit comprising:
a first field effect transistor (FET) comprising a first gate connected to the signal input, a first drain connected to a first node, and a first source connected to a ground voltage, the first node being connected to a second node through a first inductor and the second node being connected to a voltage source;
a second FET comprising a second gate connected to the first node, a second drain connected to a signal output, and a second source connected to the ground voltage, the first and second FETs amplifying the RF signal in an amplify mode;
a third FET comprising a third gate connected to an inverter which inverts a control signal, the third FET being connected in series between the first node through a first capacitor and the second node through a second capacitor, and in parallel to the first inductor; and
a bypass switch connected between the signal input and the signal output, the bypass switch being configured to activate in a bypass mode to attenuate the RF signal received from the signal input, and to prevent the first and second FETs from amplifying the RF signal.
15. The amplifing circuit of claim 14 , wherein the third FET is turned off by the inverted control signal in the amplify mode, and acts as a third capacitor connected in series with the first and second capacitors.
16. The amplifing circuit of claim 15 , wherein an impedance of the third FET and the first and second capacitors connected in series is greater than an impedance of the inductor when the third FET is turned off.
17. The amplifing circuit of claim 14 , wherein the third FET is turned on by the inverted control signal in the bypass mode, and acts as a resistor connected in series with the first and second capacitors.
18. The amplifing circuit of claim 17 , wherein an impedance of the third FET and the first and second capacitors connected in series is lower than an impedance of the inductor when the third FET is turned on.
19. The amplifing circuit of claim 18 , wherein the inductor, in combination with the third FET and the first and second capacitors connected in series, transforms the first gate of the first FET into a high reflection load across a frequency of operation when the third FET is turned on.
20. The amplifing circuit of claim 18 , wherein the lower impedance of the third FET and the first and second capacitors connected in series results in a lower voltage generated at the first node, the lower voltage driving the second FET.