SOLID STATE IMAGING DEVICE
To obtain a solid state imaging device having a data transfer function capable of outputting digital data after A/D conversion to the outside in a high speed. Each of eight stage data blocks in a data bus part has a data line pair and an amplifier part which is coupled to the data line pair. Then, the amplifier part amplifies a signal of the data line pair on an amplifier data line pair to output the amplified signal as block data outputs at timing indicated by an amplifier enable signal and an amplifier control signal. Further, the eight stage data blocks are coupled with each other from the first stage to the last stage so that the preceding stage block data outputs may be provided to the following stage data line pair as block data inputs, respectively.
1 . A solid state imaging device, comprising:
a pixel array part capable of outputting a plurality of pixel data sets in a lump after A/D conversion; and
a digital output circuit taking in the pixel data sets and sequentially outputting the pixel data sets as a final data output,
wherein the pixel data sets are divided into a predetermined number of divided pixel data groups,
wherein the digital output circuit includes a data bus part having a predetermined number of data blocks which take in the predetermined number of divided pixel data groups,
wherein each of the predetermined number of data blocks includes a data line for reading out the corresponding divided pixel data group, and an amplifier part amplifying a signal of the data line at a predetermined timing and outputting the amplified signal as a block data output,
wherein the predetermined number of data blocks are coupled with each other from the first stage to the last stage so that the block data output of a preceding stage can be provided to the data line of a following stage as a block data input, and
wherein the block data output of the data block at the last stage becomes the final data output.
2 . The solid state imaging device according to claim 1 ,
wherein the digital output circuit further includes a timing control signal generation part having a predetermined number of local counters provided corresponding to the predetermined number of data blocks, and
wherein each of the predetermined number of local counters has a control signal generation function of outputting a first timing control signal which indicates timing for sequentially reading out the pixel data in the corresponding divided pixel data group onto the data line and of outputting a second timing control signal indicating timing for amplifying the data read-out onto the data line by the amplifier part to obtain the block data output.
3 . The solid state imaging device according to claim 2 ,
wherein the digital output circuit further includes a clock distribution part distributing a predetermined number of control clocks to the predetermined number of local counters, and
wherein the clock distribution part receives a reference clock, and distributes the predetermined number of control clocks by distributing the reference clock by equal-length wirings.
4 . The solid state imaging device according to claim 3 ,
wherein the predetermined number of local counters output the first and second control signals to the predetermined number of data blocks, respectively, so as to read out the predetermined number of divided pixel data groups onto the corresponding data lines in order from the first stage to the last stage and also so as not to generate timing discontinuity when the data line to receive the read-out data is switched to the data line of the following stage.