Thin film transistor array panel and method for manufacturing the same
View Patent ↗A thin film transistor array panel according to the present invention includes: a gate line formed on a substrate and including a gate electrode; a gate insulating layer formed on the gate electrode; a mold layer formed on the gate insulating layer and having an opening overlapping the gate electrode; a semiconductor layer filled in the opening; a data line formed on the mold layer and including a source electrode contacted with the semiconductor layer; a drain electrode contacted with the semiconductor layer on the mold layer and facing the source electrode; a passivation layer formed on the data line and the drain electrode; and a pixel electrode formed on the passivation layer and connected to the drain electrode, wherein the passivation layer, the source electrode, and the drain electrode have at least one through-hole connected to the opening.
1. A method for manufacturing a thin film transistor array panel, comprising:
forming a gate line including a gate electrode on a substrate;
forming a gate insulating layer, a buffer layer, and a metal layer on the gate line;
patterning the metal layer and the buffer layer by photolithography to form a data line including a source electrode and a drain electrode, and a mold layer pattern;
forming a passivation layer having a contact hole exposing the drain electrode on the data line and the drain electrode;
forming a transparent conductive layer connected to the drain electrode through the contact hole on the passivation layer;
patterning the transparent conductive layer, the passivation layer, the source electrode, and the drain electrode by photolithography to form a pixel electrode and a through-hole exposing the mold layer pattern;
etching the exposed mold layer pattern through the through-hole to form a mold layer having an opening connected to the through-hole; and
filling a semiconductor in the opening through the through-hole.
2. The method of claim 1 , wherein
the gate insulating layer and the buffer layer are made of materials having large etch rate difference.
3. The method of claim 2 , wherein
the gate insulating layer and the buffer layer are made of the same material, and
the gate insulating layer is formed at a higher temperature than the buffer layer.
4. The method of claim 3 , wherein:
the gate insulating layer is formed at a temperature higher than 220° C., and
the buffer layer is formed at a temperature lower than 130° C.
5. The method of claim 1 , wherein,
in the forming of the mold layer,
the mold layer pattern is over-etched after exposing the gate insulating layer.
6. The method of claim 1 , wherein
the through-hole includes a first through-hole passing through the source electrode and a second through-hole passing through the drain electrode.
7. The method of claim 6 wherein
the neighboring first through-hole or the neighboring second through-hole are connected by the opening through the over-etching.
8. The method of claim 1 , wherein
the patterning of the transparent conductive layer, the passivation layer, the source electrode, and the drain electrode by photolithography to form the pixel electrode and the through-hole exposing the mold layer pattern comprises:
forming a first photosensitive film pattern including a first portion and a second portion thicker the first portion on the transparent conductive layer;
etching the transparent conductive layer, the passivation layer, the source electrode, and the drain electrode by using the first photosensitive film pattern as a mask to form the through-hole;
ashing the first photosensitive film pattern to remove the first portion; and
etching the transparent conductive layer to form the pixel electrode.
9. The method of claim 8 , wherein
the first photosensitive film pattern exposes the transparent conductive layer corresponding to the through-hole, and the second portion is disposed corresponding to the pixel electrode.