IP Library Granted Patent US 9,059,812
Granted Patent B2
US 9,059,812 · App. 12/475,676 · Granted Jun 16, 2015

MicroTCA carrier, clock card and method for providing a clock

Inventors: Shanfu Li (Shenzhen, CN); Feng Hong (Shenzhen, CN); Cheng Chen (Shenzhen, CN)
Assignee: Huawei Technologies Co., Ltd.
H04J3/0688
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Quick Facts
Patent No.
US 9,059,812
App. No.
12/475,676
Granted
Jun 16, 2015
Kind
B2
Abstract

A MicroTCA system is disclosed that includes an MCH, a clock card connected with the MCH, and multiple AMCs. The clock card includes a clock selecting unit, configured to select and output a clock source and a phase-lock unit, configured to generate a system synchronization clock according to the clock source selected by the clock selecting unit of the clock card. The MCH includes a clock drive unit, configured to drive the system synchronization clock generated by the clock card to multiple AMCs connected with the MCH. A clock card, a cascaded MicroTCA carrier, and a method for providing a clock are also provided. In this way, the implementation of the MicroTCA clock system is simplified, and the whole configuration cost of multiple cascaded MicroTCA carriers is reduced.

Claims (16)

1. A cascaded Micro Telecommunications Computing Architecture (MicroTCA) carrier, comprising:

cascaded MicroTCA carriers including at least one master-frame Micro TCA carrier and at least one slave-frame MicroTCA carrier, wherein the at least one master-frame MicroTCA carrier includes:

a clock card comprising a first clock selecting unit for selecting and outputting a first clock source, and a phase-lock unit for generating a system synchronization clock according to the first clock source selected by the first clock selecting unit;

a Micro TCA Carrier Hub (MCH) connected with a plurality of Advanced Mezzanine Cards (AMCs) and the clock card, comprising a clock drive unit for driving the system synchronization clock generated by the clock card to the plurality of AMCs connected with the MCH,

a slot, which is configured to fix the clock card, and achieve electrical communication between the clock card and the MCH,

wherein the MCH further comprises a second clock selecting unit, configured to receive AMC line clock sources from the AMCs connected with the MCH, select a second clock source from the AMC line clock sources, and send the selected second clock source to the clock card,

wherein the clock card is configured to select the first clock source from the second clock source and at least one external clock source, and wherein:

the at least one master-frame MicroTCA carrier transfers the system synchronization clock to the at least one slave-frame MicroTCA carrier; and

the at least one slave-frame MicroTCA carrier comprises at least one slave-frame MCH configured to receive the system synchronization clock from the at least one master-frame MicroTCA carrier, and drive the system synchronization clock to multiple slave-frame AMCs connected with the at least one slave-frame MCH.

2. The MicroTCA carrier of claim 1 , wherein the at least one external clock source includes a Building Integrated Timing Supply System (BITS) clock source and a Global Positioning System (GPS) clock source.

3. The MicroTCA carrier of claim 1 , wherein the at least one master-frame MicroTCA carrier further comprises at least one standby MCH and at least one standby clock card, the standby MCH is connected with the standby clock card, and the clock card and the standby clock card is synchronized through phase locking.

4. The carrier of claim 1 , wherein the at least one master-frame MicroTCA carrier further comprises:

a master-frame MCH, configured to receive and select the second clock source, transfer the selected second clock source to the clock card, receive the system synchronization clock generated by the clock card, and drive the system synchronization clock to each master-frame AMC connected with the master-frame MCH.

5. The carrier of claim 1 , wherein:

one of the clock card and the master-frame MCH has a cascaded output interface for outputting the system synchronization clock in a cascading way; and

the slave-frame MCH has a cascaded input interface for receiving the system synchronization clock.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2022
From: HUAWEI TECHNOLOGIES CO., LTD.
To: XFUSION DIGITAL TECHNOLOGIES CO., LTD.
Reel/Frame 058682/0312 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2009
From: LI, SHANFU; HONG, FENG; CHEN, CHENG
To: HUAWEI TECHNOLOGIES CO., LTD.
Reel/Frame 023247/0444 →
Priority Claims (1)
CN 2007 1 0029656 · Aug 8, 2007 · national
Continuity (2)
Continuation PCTCN2008071829 · Jul 31, 2008
Related Publication 20100005333A1 · Jan 7, 2010