IP Library Granted Patent US 7,984,242
Granted Patent B2
US 7,984,242 · App. 12/476,109 · Granted Jul 19, 2011

Program thread syncronization

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Quick Facts
Patent No.
US 7,984,242
App. No.
12/476,109
Granted
Jul 19, 2011
Kind
B2
Abstract

A barrier for synchronizing program threads for a plurality of processors includes a filter configured to be coupled to a plurality of processors executing a plurality of threads to be synchronized. The filter is configured to monitor and selectively block fill requests for instruction cache lines. A method for synchronizing program threads for a plurality of processors includes configuring a filter to monitor and selectively block fill requests for instruction cache lines for a plurality of processors executing a plurality of threads to be synchronized.

Claims (24)

1. A system for synchronizing program threads for a plurality of processors comprising:

a filter configured to be coupled to a plurality of processors executing a plurality of threads to be synchronized; and

in which said filter is configured to monitor and selectively block fill requests for instruction cache lines corresponding to the threads to be synchronized.

2. The system of claim 1 , in which said filter is configured to monitor arrival at a barrier procedure call of a first thread and, upon said barrier procedure call of said first thread, render unavailable an instruction cache line for each of a group of threads, including said first thread, that are to be synchronized.

3. The system of claim 1 , in which said filter selectively halts execution of a thread by selectively rendering a corresponding instruction cache line unavailable and resumes executing of that thread by selectively rendering the cache line available.

4. The system of claim 1 , in which the filter comprises a table listing points at which said threads are to be synchronized.

5. The system of claim 4 , in which the filter is configured to monitor an operating system to identify context changes by associating process identifications of threads to contexts.

6. The system of claim 5 , in which the filter is configured to block fill requests for each processor according to a process identification for a thread currently executing on that processor.

7. The system of claim 1 , in which said filter comprises a plurality of filter elements, each of which is associated with one of said processors, and is connected between an interconnect and a cache memory.

8. The system of claim 7 , in which each said filter element comprises a table listing points at which said threads are be synchronized for which synchronization is to be performed by that filter element.

9. A method for synchronizing program threads for a plurality of processors comprising:

configuring a filter to monitor and selectively block fill requests for instruction cache lines for a plurality of processors executing a plurality of threads to be synchronized.

10. The method of claim 9 , further comprising configuring said filter to monitor arrival at a barrier procedure call of a first thread and, upon said arrival of said first thread, render unavailable an instruction cache line for each of a group of threads, including said first thread, that are to be synchronized.

11. The method of claim 9 , further comprising, with said filter, selectively halting execution of a thread by selectively rendering a corresponding instruction cache line unavailable and resuming executing of that thread by selectively rendering the cache line available.

12. The method of claim 9 , further comprising configuring said filter with a table listing points at which said threads are to be synchronized.

13. The method of claim 12 , further comprising configuring said filter to monitor an operating system to identify context changes by associating process identifications of threads to contexts.

14. The method of claim 13 , further comprising configuring said filter to block fill requests for each processor according to a process identification for a thread currently executing on that processor.

15. The method of claim 14 , further comprising, with said filter, blocking fill requests by invalidating a cache line for said thread currently executing on that processor.

16. The method of claim 9 , in which said filter comprises a plurality of filter elements, each of which is associated with one of said processors, and is connected between an interconnect and a cache memory.

17. The method of claim 16 , in which each said filter element comprises a table listing points at which said threads are be synchronized for which synchronization is to be performed by that filter element.

18. A filter for synchronizing program threads for a plurality of processors comprising:

said filter configured to be coupled to a plurality of processors executing a plurality of threads to be synchronized, where said filter is configured to selectively halt execution of any of said threads until said threads have been synchronized.

19. The filter of claim 18 , in which the filter is configured to monitor an operating system to identify context changes by associating process identifications of threads to contexts.

20. The filter of claim 19 , in which the filter is configured to block fill requests for each processor according to a process identification for a thread currently executing on that processor.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2022
From: OT PATENT ESCROW, LLC
To: VALTRUS INNOVATIONS LIMITED
Reel/Frame 060005/0600 →
PATENT ASSIGNMENT, SECURITY INTEREST, AND LIEN AGREEMENT Recorded Jan 26, 2021
From: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP; HEWLETT PACKARD ENTERPRISE COMPANY
To: OT PATENT ESCROW, LLC
Reel/Frame 055269/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2015
From: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
To: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Reel/Frame 037079/0001 →