Bi-directional multi-drop bus memory system
View Patent ↗A bus system includes a plurality of stubs; a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules; a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs, wherein the first and the second serial loads are determined to be impedance matched at each transmission line terminal of the stubs.
1. A bus system, comprising:
a plurality of stubs;
a plurality of connectors, each of which is serially coupled to a corresponding one of the stubs;
a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and
a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs,
wherein the first and second serial loads are determined by the following equation:
Zc
[
n
]
=
nZ
0
Zb
[
n
]
=
Z
0
/
n
,
Zb
[
0
]
=
0
where, Zc[n] denotes the first serial loads; the Zb[n] denotes the second serial loads; n denotes an index allocated for each of the stubs and has ‘0’ or a positive integer; and Z0 denotes a characteristic impedance of the bus system.
2. The bus system of claim 1 , wherein a plurality of memory modules, each of which includes at least one memory chip, are correspondingly coupled to the stubs through the corresponding connectors; and a memory controller is coupled to the bus system.
3. The bus system of claim 2 , wherein the memory chips and the memory controller are on-die terminated.
4. The bus system of claim 2 , wherein each of the memory chips includes a signal driver that are line-matched with the memory modules.
5. The bus system of claim 2 , wherein the memory controller includes a signal driver that is line-matched with the bus system.
6. The bus system of claim 2 , wherein the first and second serial loads are implemented with a printed circuit board (PCB) embedded load.
7. The bus system of claim 2 , wherein each of the memory modules includes:
a first load, coupled to a corresponding one of the connectors, having a characteristic impedance of the memory modules;
a second load, coupled to the first load, having an equivalent impedance with the first load;
a first memory chip coupled to the second load;
a third load, coupled in parallel with the second load, having the equivalent impedance with the first load;
a second memory chip coupled to the third load; and
a fourth load, serially coupled between the first load and a common node of the second and third loads, having a half impedance of the first load.
8. A bus system, comprising:
a plurality of stubs;
a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules;
a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors;
a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs; and
a parallel resistor of
Z
1
Z
2
Z
2
-
Z
1
connected to a final one of the stubs,
wherein the first and second serial loads are determined by the following equation:
Zc
[
n
]
=
nZ
1
,
Zc
[
0
]
=
0
Zb
[
n
]
=
Z
1
2
(
n
+
1
)
Z
1
+
Z
2
where, Zc[n] denotes the first serial loads; the Zb[n] denotes the second serial loads; n denotes an index allocated for each of the stubs and has a positive integer; Z1 denotes a characteristic impedance of the bus system; and Z2 denotes a characteristic impedance of the memory module.
9. The bus system of claim 8 , wherein an on-die terminated memory controller is coupled to the bus system.
10. The bus system of claim 8 , wherein each of the memory modules includes at least one on-die terminated memory chip that is line-matched with the memory module.
11. The bus system of claim 9 , wherein the on-die terminated memory controller includes a signal driver that is line-matched with the bus system.
12. The bus system of claim 8 , wherein the first and second serial loads are implemented with a PCB embedded load.
13. The bus system of claim 8 , wherein each of the memory modules includes:
a first load, coupled to a corresponding one of the connectors, having a characteristic impedance of the memory modules;
a second load, coupled to the first load, having an equivalent impedance with the first load;
a first memory chip coupled to the second load;
a third load, coupled in parallel with the second load, having the equivalent impedance with the first load;
a second memory chip coupled to the third load; and
a fourth load, serially coupled between the first load and a common node of the second and third loads, having a half impedance of the first load.
14. A bus system, comprising:
a plurality of stubs;
a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules;
a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and
a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs,
wherein the first and second serial loads are determined by the following equation:
Zc
[
n
]
=
(
n
+
1
)
Z
1
-
Z
2
Zb
[
n
]
=
Z
1
n
where, Zc[n] denotes the first serial loads; the Zb[n] denotes the second serial loads; n denotes an index allocated for each of the stubs and has ‘0’ or a positive integer; Z1 denotes a characteristic impedance of the bus system; and Z2 denotes a characteristic impedance of the memory module.
15. The bus system of claim 14 , wherein an on-die terminated memory controller is coupled to the bus system.
16. The bus system of claim 14 , wherein each of the memory modules includes at least one on-die terminated memory chip that is line-matched with the memory module.
17. The bus system of claim 15 , wherein the on-die terminated memory controller includes a signal driver that is line-matched with the bus system.
18. The bus system of claim 14 , wherein the first and second serial loads are implemented with a PCB embedded load.
19. The bus system of claim 14 , wherein each of the memory modules includes:
a first load, coupled to a corresponding one of the connectors, having a characteristic impedance of the memory modules;
a second load, coupled to the first load, having an equivalent impedance with the first load;
a first memory chip coupled to the second load;
a third load, coupled in parallel with the second load, having the equivalent impedance with the first load;
a second memory chip coupled to the third load; and
a fourth load, serially coupled between the first load and a common node of the second and third loads, having a half impedance of the first load.
20. A memory system, comprising:
a plurality of stubs;
a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules;
a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and
a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs,
wherein the first and second serial loads are determined by the following equation:
Zc
[
n
]
=
nZ
0
Zb
[
n
]
=
Z
0
/
n
,
Zb
[
0
]
=
0
where, Zc[n] denotes the first serial loads; the Zb[n] denotes the second serial loads; n denotes an index allocated for each of the stubs and has ‘0’ or a positive integer; and Z0 denotes the characteristic impedance of the transmission line.
21. A memory system, comprising:
a plurality of stubs;
a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules;
a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors;
a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs; and
a parallel resistor of
Z
1
Z
2
Z
2
-
Z
1
connected to the final stub,
wherein the first and second serial loads are determined by the following equation:
Zc
[
n
]
=
n
Z
1
,
Zc
[
0
]
=
0
Zb
[
n
]
=
Z
1
2
(
n
+
1
)
Z
1
+
Z
2
where, Zc[n] denotes the first serial loads; the Zb[n] denotes the second serial loads; n denotes an index allocated for each of the stubs and has a positive integer; Z1 denotes the characteristic impedance of the transmission line; and Z2 denotes a characteristic impedance of the memory module.
22. A memory system, comprising:
a plurality of stubs;
a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules;
a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and
a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs,
wherein the first and second serial loads are determined by the following equation:
Zc
[
n
]
=
(
n
+
1
)
Z
1
-
Z
2
Zb
[
n
]
=
Z
1
n
where, Zc[n] denotes the first serial loads; the Zb[n] denotes the second serial loads; n denotes an index allocated for each of the stubs and has ‘0’ or a positive integer; Z1 denotes the characteristic impedance of the transmission line; and Z2 denotes a characteristic impedance of the memory module.