THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF

1 . A thin film transistor array panel, comprising:

a substrate;

a gate line disposed on the substrate, the gate line comprising a gate electrode;

a gate insulating layer disposed on the gate line;

a semiconductor disposed on the gate insulating layer;

a data line disposed on the semiconductor, the data line comprising a source electrode;

a drain electrode disposed on the semiconductor, the drain electrode facing the source electrode;

a passivation layer disposed on the data line and the drain electrode;

an upper layer disposed on the passivation layer, the upper layer comprising a metal oxide semiconductor or a transparent conductive oxide; and

a pixel electrode disposed on the upper layer, the pixel electrode connected to the drain electrode,

wherein the upper layer comprises a first upper layer pattern overlapping with the pixel electrode.

2 . The thin film transistor array panel of claim 1 , wherein

the boundary of the first upper layer pattern is aligned with the boundary of the pixel electrode inside the boundary of the pixel electrode.

3 . The thin film transistor array panel of claim 2 , wherein

the first upper layer pattern comprises a first upper layer opening exposing a portion of the drain electrode.

4 . The thin film transistor array panel of claim 3 , wherein

the passivation layer comprises a first passivation layer pattern overlapping with the first upper layer pattern.

5 . The thin film transistor array panel of claim 4 , wherein

the boundary of the first passivation layer pattern is aligned with the boundary of the first upper layer pattern outside the boundary of the first upper layer pattern.

6 . The thin film transistor array panel of claim 5 , wherein

the width between the boundary of the first passivation layer pattern and the boundary of the first upper layer pattern is more than about 0.2 μm.

7 . The thin film transistor array panel of claim 1 , wherein

the upper layer comprises a second upper layer pattern, and

the second upper layer pattern overlaps the gate line, the gate electrode, and the data line, and is separated from the first upper layer pattern.

8 . The thin film transistor array panel of claim 7 , wherein

the boundary of the second upper layer pattern is aligned with the boundary of a region occupied with the gate line, the gate electrode, and the data line outside the boundary of the region.

9 . The thin film transistor array panel of claim 8 , wherein

the passivation layer comprises a second passivation layer pattern overlapping with the second upper layer pattern.

10 . The thin film transistor array panel of claim 9 , wherein

the boundary of the second passivation layer pattern is aligned with the boundary of the second upper layer pattern outside the boundary of the second upper layer pattern.

11 . The thin film transistor array panel of claim 10 , wherein

the width between the boundary of the second passivation layer pattern and the boundary of the second upper layer pattern is more than about 0.2 μm.

12 . The thin film transistor array panel of claim 1 , wherein

the data line comprises an end portion, the upper layer comprises a third upper layer opening, and the end portion of the data line is disposed inside the third upper layer opening.

13 . The thin film transistor array panel of claim 12 , wherein

the semiconductor comprises an end portion, and the end portion of the semiconductor has substantially the same plane shape as the end portion of the data line.

14 . The thin film transistor array panel of claim 1 , wherein

the gate line comprises an end portion, the upper layer comprises a fourth upper layer opening, and the end portion of the gate line is disposed inside the fourth upper layer opening.

15 . The thin film transistor array panel of claim 1 , wherein

the gate line is connected to the upper layer through a contact hole.

16 . A method for manufacturing a thin film transistor array panel, comprising:

forming a gate line on a substrate, the gate line comprising a gate electrode;

forming a gate insulating layer on the gate line;

forming a semiconductor on the gate insulating layer;

forming a data line on the semiconductor;

simultaneously patterning the semiconductor and the data line;

forming a passivation layer on the data line;

forming an upper layer on the passivation layer;

forming a photosensitive film pattern on the upper layer;

etching the upper layer using the photosensitive film pattern as a mask;

etching the passivation layer; and

forming a pixel electrode on the passivation layer,

wherein the upper layer comprises a metal oxide semiconductor or a transparent conductive oxide, and comprises a first upper layer pattern overlapping with the pixel electrode.

17 . The method of claim 16 , wherein

the photosensitive film pattern comprises a first photosensitive film pattern and a second photosensitive film pattern, and

the first photosensitive film pattern and the second photosensitive film pattern have different thicknesses from each other and are spaced apart from each other.

18 . The method of claim 17 , wherein

the etching of the upper layer comprises forming the first upper layer pattern inside the boundary of the first photosensitive film pattern.

19 . The method of claim 18 , wherein

the etching of the passivation layer comprises forming a first passivation layer pattern outside the boundary of the first upper layer pattern.

20 . The method of claim 17 , wherein

the second photosensitive film pattern covers a region occupied with the gate line, the gate electrode, and the data line.

21 . The method of claim 20 , wherein

the etching of the upper layer comprises forming a second upper layer pattern inside the boundary of the second photosensitive film pattern.

22 . The method of claim 21 , wherein

the etching of the passivation layer comprises forming a second passivation layer pattern outside the boundary of the second upper layer pattern.