Thin film magnetic memory device writing data with bidirectional current
View Patent ↗An end of a selected bit line in a selected column is electrically coupled to an end of a corresponding current return line by one of first and second write column select gates, which are selectively turned on in response to results of column selection. A data write circuit sets the other end of the selected bit line and the other end of the current return line to one and the other of a power supply voltage and a ground voltage in accordance with a level of write data via one of first and second data buses and an inverted data bus, respectively.
1. A semiconductor device comprising:
a plurality of memory cells each storing data by being magnetized in a direction corresponding to an applied data write magnetic field;
a plurality of bit lines arranged corresponding to predetermined sections of said plurality of memory cells, respectively; and
data write circuits for supplying, in a direction corresponding to write data, a data write current producing said data write magnetic field to at least one of said plurality of bit lines, wherein
said data write circuit includes a plurality of first drive circuits arranged corresponding to said plurality of bit lines, respectively, and each configured to drive a voltage on one end side of the corresponding bit line,
said plurality of bit lines are divided into a plurality of groups,
each of said plurality of groups has said bit lines of X (X: integer larger than one) in number electrically coupled on the other end side via a short-circuit node,
said data write circuit further includes a plurality of second drive circuits arranged corresponding to said plurality of groups for driving voltages on said corresponding short-circuit nodes, respectively,
at least one of said plurality of first drive circuits corresponding to a selected memory cell drives the corresponding one end side with one of first and second voltages according to said write data, and
at least one of said plurality of second drive circuits corresponding to said selected memory cell drives the corresponding short-circuit node with the other of said first and second voltages according to said write data.
2. The semiconductor device according to claim 1 , wherein
each of said memory cells includes:
a magneto-resistance element having an electric resistance variable in accordance with a magnetization direction, and
an access element connected between a predetermined voltage and the corresponding bit line and arranged in series with said magneto-resistance element;
said access element at least in the selected memory cell is turned on during data reading; and
said semiconductor device comprises:
a read data line extending in a direction crossing said plurality of bit lines, and arranged corresponding to said the other end side of said plurality of bit lines, and
read select gates arranged corresponding to said plurality of groups, respectively, and each selectively connecting the corresponding short-circuit node to said read data line during said data reading.
3. A semiconductor device comprising:
a memory array including a plurality of magnetic memory cells arranged in rows and columns, each of said plurality of magnetic memory cells including a magneto-resistance element having either a first or second resistance value according to a level of storage data that is written in response to an applied magnetic field generated by first and second data write currents, and an access element connected with said magneto-resistance element in series:
a plurality of write word lines provided corresponding to the respective rows of the magnetic memory cells, and passing said first data write current therethrough in a data write operation;
a plurality of bit lines provided corresponding to the respective columns of the magnetic memory cells, and passing said second data write current through in said data write operation; and
a plurality of write drive circuits arranged corresponding to one end side of said plurality of bit lines, respectively, and supplying said second data write current in a direction corresponding to write data to said bit lines, wherein
said plurality of bit lines are divided into a plurality of bit line pairs, each of said plurality of bit line pairs electrically coupled on the other end side via a short-circuit node; and
said semiconductor device further comprises:
a read data bus arranged corresponding to said the other end side of said plurality of bit lines, and
a plurality of read select gates arranged corresponding to said short-circuit node of said plurality of bit line pairs, respectively, and each selectively connecting the corresponding shortcircuit node to said read bus in a data read operation.
4. The semiconductor device according to claim 3 , wherein said plurality of bit line pairs are formed at a first wiring layer.
5. The semiconductor device according to claim 4 , wherein said short-circuit node is formed at said first wiring layer.
6. The semiconductor device according to claim 3 , wherein said read data bus is arranged to extend along a direction crossing said plurality of bit lines.
7. The semiconductor device according to claim 3 , wherein said plurality of read select gates are arranged across the memory array from said plurality of write drive circuits and disposed in the other end side of said plurality of bit lines.