Method and system for implementing energy efficient ethernet techniques in a MACSec enabled PHY
Aspects of a method and system for implementing energy efficient Ethernet techniques in a MACSec enabled PHY are provided. In this regard, an Ethernet PHY comprising memory may be operable to perform packet processing functions comprising MACSec protocol processing and energy efficient Ethernet (EEE) processing. In this regard, the memory may be utilized for implementing the MACSec protocol processing and energy efficient Ethernet (EEE) processing. The Ethernet packet processing functions may comprise packet inspection, packet generation, and packet modification. The energy efficient Ethernet (EEE) processing may comprise generating and/or inspecting messages for controlling when to transition into and out-of an energy-saving mode. The Ethernet PHY may be operable to monitor signals and/or conditions within the Ethernet PHY and control transitions into and out-of an energy-saving mode based on the monitored signals and/or conditions. The energy saving mode may comprise a low power idle mode and/or a subset PHY mode.
1. A method for networking, the method comprising:
performing by one or more circuits in a first Ethernet physical layer device (PHY), wherein the first Ethernet PHY includes a MACSec module configured for communication with a second Ethernet PHY in a link partner using a MACSec protocol, the MACSec module including a memory:
receiving information from the second Ethernet PHY, the received information enabling the first Ethernet PHY to determine energy saving capabilities of the second Ethernet PHY; and
allocating, based on the determined energy saving capabilities of the second Ethernet PHY, a portion of the memory for buffering of one or more Ethernet packets that are awaiting communication onto the link concurrent with the first Ethernet PHY transitioning between a first data rate and a second data rate, at least one of the first data rate and the second data rate used in an energy saving mode of the first Ethernet PHY.
2. The method according to claim 1 , further performing, by the one or more circuits, generating and/or inspecting, in the first Ethernet PHY, messages for controlling when the transitioning occurs.
3. The method according to claim 1 , wherein the allocating comprises allocating a first portion of the memory for MACSec protocol processing and a second portion of the memory for energy efficient Ethernet (EEE) processing.
4. The method according to claim 3 , wherein the first portion of the memory for MACSec protocol processing is allocated prior to the second portion of the memory for energy efficient Ethernet (EEE) processing.
5. The method according to claim 3 , wherein the second portion of the memory for energy efficient Ethernet (EEE) processing is allocated prior to the first portion of the memory for MACSec protocol processing.
6. The method according to claim 1 , wherein one of the first and second data rates is enabled by a low power idle mode.
7. The method according to claim 1 , wherein one of the first and second data rates is enabled by a subset PHY mode.
8. The method according to claim 1 , wherein the received information from the second Ethernet PHY enables the first Ethernet PHY to determine a length of time for the second Ethernet PHY to transition between the first data rate and the second data rate.
9. The method according to claim 1 , wherein the received information from the second Ethernet PHY enables the first Ethernet PHY to determine an energy saving mode supported by the second Ethernet PHY.
10. The method according to claim 1 , wherein the received information from the second Ethernet PHY enables the first Ethernet PHY to determine an amount of buffering that the second Ethernet PHY can allocate for transitions between the first data rate and the second data rate.
11. A device for networking, comprising:
one or more circuits for use in a first Ethernet physical layer device (PHY), wherein the first Ethernet PHY includes a MACSec module configured for communication with a second Ethernet PHY in a link partner using a MACSec protocol, the MACSec module including a memory, wherein the one or more circuits are operable to:
receive information from the second Ethernet PHY, the received information enabling the first Ethernet PHY to determine energy saving capabilities of the second Ethernet PHY; and
allocate, based on the determined energy saving capabilities of the second Ethernet PHY, a portion of the memory for buffering of one or more other Ethernet packets that are awaiting communication onto the link concurrent with the first Ethernet PHY transitioning between a first data rate and a second data rate, at least one of the first data rate and the second data rate used in an energy saving mode of the first Ethernet PHY.
12. The device according to claim 11 , wherein the one or more circuits are further operable to generate and/or inspect, in the first Ethernet PHY, messages for controlling when the transitioning occurs.
13. The device according to claim 11 , wherein the one or more circuits are operable to allocate a first portion of the memory for MACSec protocol processing and a second portion of the memory for energy efficient Ethernet (EEE) processing.
14. The device according to claim 13 , wherein the first portion of the memory for MACSec protocol processing is allocated prior to the second portion of the memory for energy efficient Ethernet (EEE) processing.
15. The device according to claim 13 , wherein the second portion of the memory for energy efficient Ethernet (EEE) processing is allocated prior to the first portion of the memory for MACSec protocol processing.
16. The device according to claim 11 , wherein one of the first and second data rates is enabled by a low power idle mode.
17. The device according to claim 11 , wherein one of the first and second data rates is enabled by a subset PHY mode.
18. The device according to claim 11 , wherein the received information from the second Ethernet PHY enables the first Ethernet PHY to determine a length of time for the second Ethernet PHY to transition between the first data rate and the second data rate.
19. The device according to claim 11 , wherein the received information from the second Ethernet PHY enables the first Ethernet PHY to determine an energy saving mode supported by the second Ethernet PHY.
20. The device according to claim 11 , wherein the received information from the second Ethernet PHY enables the first Ethernet PHY to determine an amount of buffering that the second Ethernet PHY can allocate for transitions between the first data rate and the second data rate.