Synchronous delay-line amplification technique

1. Electronic circuitry enabling an open-loop switching amplifier receiving incoming data to achieve synchronous operation, comprising:

a ring oscillator based upon a tapped delay line;

a decoder having an input connected to the taps of the delay line and an output forming the more significant data to a comparator;

a counter clocked by the ring oscillator; and

wherein the comparator periodically compares the more significant data to the value of the counter to form a pulsewidth modulated output waveform.

2. The circuitry of claim 1 , wherein the tapped delay line has 8 taps.

3. A circuit comprising:

an oscillator including a tapped delay line;

a decoder coupled to the tapped delay line and configured to generate a first output;

a counter coupled to the oscillator and configured to generate a second output; and

a comparator configured to receive the first and second outputs and to generate a pulse-width modulated output signal in response to the first and second outputs.

4. The circuit of claim 3, wherein the oscillator comprises a ring oscillator.

5. The circuit of claim 3, wherein the first output is based, at least in part, on signals received from a plurality of taps of the tapped delay line.

6. The circuit of claim 3, wherein the counter is configured to increment in response to a signal received at one tap of the oscillator, and wherein the second output is based on a count of the counter.

7. The circuit of claim 3, wherein the comparator is further configured to:

receive input data and compare the input data with a signal based on the first and second outputs; and

generate the pulse-width modulated output signal based, at least in part, on the comparison.

8. The circuit of claim 3, wherein the first and second outputs comprise binary numbers.

9. The circuit of claim 3, wherein the first output is configured to change at a first rate and the second output is configured to change at a second rate, and wherein the first rate is faster than the second rate.

10. The circuit of claim 3, wherein the comparator comprises less significant inputs and more significant inputs, and wherein the decoder is further coupled to the less significant inputs and the counter is further coupled to the more significant inputs.

11. The circuit of claim 3, wherein the counter is further configured to reset in response to said generation of the pulse-width modulated output signal.

12. A method for generating a pulse-width modulated output signal, the method comprising:

driving inputs of a comparator through sequential binary states, each state having a first and a second group of bits, wherein the first group of bits is based, at least in part, on signals received from taps of an oscillator delay line, and wherein the second group of bits is based, at least in part, on counts from a counter configured to be incremented by an oscillator;

comparing received data with the comparator inputs; and

generating the pulse-width modulated output signal based, at least in part, on the comparison.

13. The method of claim 12, wherein the oscillator comprises a ring oscillator.

14. The method of claim 12, wherein the first group of bits changes at a faster rate than the second group of bits.

15. The method of claim 12, wherein a width of the pulse-width modulated output signal is based, at least in part, on the comparison.

16. The method of claim 12, further comprising stopping the oscillator and the counter at an end of a period of the pulse-width modulated output signal.

17. The method of claim 12, further comprising, in response to receiving a period start strobe signal, latching input data and starting the oscillator and the counter.