IP Library Granted Patent US 8,312,202
Granted Patent B1
US 8,312,202 · App. 12/483,970 · Granted Nov 13, 2012

Kernel acceleration technology for virtual machine optimization

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Quick Facts
Patent No.
US 8,312,202
App. No.
12/483,970
Granted
Nov 13, 2012
Kind
B1
Abstract

A system, method and computer program product for optimizing handling of guest code in a Virtual Machine include means for identifying, in the guest code, a predetermined pattern that includes privileged but unsafe instructions and an instruction that raises an exception; means for executing the guest code in a native mode; means for, upon encountering the instruction that raise the exception, transferring control to a Virtual Machine Monitor; means for emulating the pattern in the Virtual Machine Monitor; and means for rolling back the effects of privileged but unsafe instructions and any intervening instructions to ensure correct Virtual Machine Monitor context. The pattern can include, for example, a privileged but unsafe instruction, followed by safe instructions, followed by an exception raising instruction, followed by safe instructions, followed by a privileged but unsafe instruction. Optionally, the most frequently occurring patterns can be placed in a cache, for use by the Virtual Machine Monitor to verify their presence in the guest code.

Claims (38)

1. A method for optimizing handling of guest code in a Virtual Machine, comprising:

(a) identifying, in the guest code, unsafe instructions;

(b) adding, to the guest code, instructions that raise exceptions in proximity to the unsafe instructions, such that the unsafe instructions and the instructions that raise exceptions form a predetermined pattern;

(c) executing the modified guest code in a native mode;

(d) upon encountering the instruction that raises the exception, transferring control to a Virtual Machine Monitor;

(e) in the Virtual Machine Monitor, detecting the pattern; and

(f) rolling back the effects of unsafe instructions and any intervening instructions to ensure correct guest OS code context.

2. The method of claim 1 , wherein the pattern includes a privileged but unsafe instruction, followed by safe instructions, followed by an exception raising instruction, followed by safe instructions, followed by a privileged but unsafe instruction.

3. The method of claim 1 , further comprising placing most frequently occurring patterns in a cache, for use by the Virtual Machine Monitor to verify pattern presence in the guest code.

4. The method of claim 1 , wherein the event is any of an exception, a software interrupt, and a break in the guest code native execution.

5. The method of claim 1 , wherein an effective absolute address in the EIP register is preserved from unmodified guest code to the modified guest code.

6. A method for optimizing handling of guest code in a Virtual Machine, comprising:

(a) identifying, in the guest code, unsafe instructions that do not have a breakpoint in their proximity;

(b) adding breakpoints to the guest code, such that the unsafe instructions and the breakpoints form a predetermined pattern;

(c) executing the modified guest code in a native mode;

(d) upon encountering the breakpoint, transferring control to a Virtual Machine Monitor;

(e) in the VMM, analyzing the VM context, and, based on the VM context, (i) generating bypassing code, which does not contain unsafe instructions, or (ii) executing of the unmodified original guest code, or (iii) executing different code that ensures that the execution of the unsafe instructions becomes safe;

(f) in the Virtual Machine Monitor, rolling back the effects of unsafe instructions and any intervening instructions to ensure correct guest OS code context.

7. The method of claim 6 , further comprising inserting instructions that raise exceptions into the analyzed code, near privileged but unsafe instructions that otherwise do not have, in their neighborhood, an instruction that raises an exception.

8. The method of claim 7 , further comprising setting the Virtual Machine Monitor to treat at least one instruction that otherwise does not raise exceptions as one that raises an exception.

9. The method of claim 6 , wherein the replaced instructions are emulated.

10. The method of claim 6 , wherein the replaced instructions are rolled back.

11. The method of claim 10 , wherein the replaced instructions occur in the guest code prior to the pattern.

12. The method of claim 6 , wherein an effective absolute address in the EIP register is preserved from unmodified guest code to the modified guest code.

13. A method for optimizing handling of guest code in a Virtual Machine, comprising:

(a) identifying, in the guest code, unsafe instructions;

(b) adding, to the guest code, instructions that raise exceptions, such that the unsafe instructions and the instructions that raise exceptions form a predetermined pattern;

(c) executing the modified guest code in a native mode,

wherein an effective absolute address in the EIP register is preserved from unmodified guest code to the modified guest code;

(d) upon encountering the instruction that raises the exception, transferring control to a Virtual Machine Monitor;

(e) in the Virtual Machine Monitor, detecting the pattern; and

(f) rolling back the effects of unsafe instructions and any intervening instructions to ensure correct guest OS code context.

14. The method of claim 13 , wherein an effective absolute address in the EIP register is preserved from unmodified guest code to the modified guest code.

15. A non-transitory computer useable storage medium having computer program logic recorded thereon for executing on a processor, for performing the method of claim 13 .

16. A system for optimizing handling of guest code in a Virtual Machine, the system comprising:

a processor;

a memory coupled to the processor;

computer code loaded into the memory for performing the steps of claim 13 .

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Jul 18, 2019
From: UBS AG, STAMFORD BRANCH, AS ADMINISTRATIVE AND COLLATERAL AGENT
To: COREL CORPORATION; CLEARSLIDE, INC.; PARALLELS INTERNATIONAL GMBH
Reel/Frame 049787/0073 →
RELEASE OF SECURITY INTEREST RECORDED AT : REEL 047973 FRAME 0797 Recorded Jul 17, 2019
From: UBS AG, STAMFORD BRANCH
To: PARALLELS INTERNATIONAL GMBH
Reel/Frame 049773/0590 →
SECURITY INTEREST Recorded Dec 21, 2018
From: PARALLELS INTERNATIONAL GMBH
To: UBS AG, STAMFORD BRANCH
Reel/Frame 047973/0797 →
MERGER Recorded Jan 30, 2018
From: PARALLELS IP HOLDINGS GMBH
To: PARALLELS INTERNATIONAL GMBH
Reel/Frame 045193/0679 →
RELEASE OF SECURITY INTEREST Recorded Dec 14, 2015
From: SILICON VALLEY BANK
To: PARALLELS HOLDINGS LTD. (F/K/A SWSOFT HOLDINGS LTD.)
Reel/Frame 037289/0685 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2011
From: PARALLELS SOFTWARE INTERNATIONAL, INC.
To: PARALLELS HOLDINGS, LTD.
Reel/Frame 027467/0328 →
SECURITY AGREEMENT Recorded Jun 23, 2011
From: PARALLELS HOLDINGS LTD. (F/K/A SWSOFT HOLDINGS LTD.)
To: SILICON VALLEY BANK
Reel/Frame 026480/0957 →
SECURITY AGREEMENT Recorded Apr 3, 2010
From: PARALLELS HOLDINGS, LTD.
To: SILICON VALLEY BANK
Reel/Frame 024182/0685 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2009
From: KORYAKIN, ALEXEY B.; DOBROVOLSKIY, NIKOLAY N.; OMELYANCHUK, ANDREY A.
To: PARALLELS SOFTWARE INTERNATIONAL, INC.
Reel/Frame 022821/0524 →