Method of fabricating a thin film transistor array substrate
View Patent ↗A method of fabricating a thin film transistor array substrate is presented. The method entails forming a gate interconnection line on an insulating substrate, forming a gate insulating layer on the gate interconnection line, forming a semiconductor layer and a data interconnection line on the semiconductor layer, sequentially forming multiple passivation layers, etching the passivation layers down to a drain electrode that is an extension of the data interconnection line. The portion of the drain electrode that is exposed at this stage is a part of the drain electrode-pixel electrode contact portion. A pixel electrode is formed connected to the drain electrode. Two of the passivation layers have the same composition but are processed at different temperatures. A thin film transistor prepared in the above manner is also presented.
1. A method of fabricating a thin film transistor (TFT) array substrate, the method comprising:
forming a gate interconnection line on an insulating substrate, the gate interconnection line comprising a gate line and a gate electrode;
forming a gate insulating layer on the gate interconnection line;
forming a semiconductor layer and a data interconnection line on the semiconductor layer, the data interconnection line comprising a data line, a source electrode, and a drain electrode;
sequentially forming a first passivation layer, a second passivation layer and a third passivation layer;
etching the third passivation layer, the second passivation layer and the first passivation layer, and exposing a drain electrode of a drain electrode-pixel electrode contact portion; and
forming a pixel electrode connected to the drain electrode,
wherein a composition of the second passivation layer and third passivation layer is the same, and a process temperature for the third passivation layer is higher than that of the second passivation layer and wherein the first passivation layer comprises silicon oxide or silicon oxy-nitride and the second passivation layer, and the third passivation layer comprises silicon nitride.
2. The method of claim 1 , wherein the semiconductor layer includes an oxide semiconductor including at least one of the Hafnium, Zinc, Indium, Gallium, and Tin.
3. The method of claim 1 , wherein the etching of the second passivation layer, and the third passivation layer further comprises isotropic etching.
4. The method of claim 3 , wherein the side of the second passivation layer corresponding to the contact portion comprises an undercut in the etching process.
5. The method of claim 3 , wherein etching the third passivation layer, the second passivation layer and the first passivation layer comprises:
forming a photo-resist on the third passivation layer;
exposing the photo resist and developing the photo resist;
etching the second passivation layer, and the third passivation layer using the photoresist pattern as a etching mask;
wherein the side of the second passivation layer corresponding to the contact portion is etched more resulting in an undercut.
6. The method of claim 5 , wherein the forming a pixel electrode comprises:
exposing the third passivation layer by removing the photoresist pattern used as an etching mask;
depositing a transparent electrode on the third passivation layer;
etching the third passivation layer and the second passivation layer using a plasma enhanced (PE) chemical etching mode.