IP Library Granted Patent US 8,889,482
Granted Patent B2
US 8,889,482 · App. 12/484,221 · Granted Nov 18, 2014

Methods to fabricate integrated circuits by assembling components

Inventor: Jayna Sheats (Palo Alto, CA)
H01L24/45H01L2224/85001H01L2224/1131H01L2224/45015H01L2924/0105H01L2924/14H01L2224/81191H01L2924/01047H01L2224/48472H01L2924/01014H01L25/18H01L2924/19042H01L2225/06524H01L2224/81801H01L2224/45124H01L2225/06513H01L24/11H01L2224/05599H01L2924/01075H01L2924/01031H01L24/78H01L2224/45147H01L2924/19043H01L2225/06579H01L2924/19041H01L2225/06506H01L2924/014H01L2224/13099H01L2924/01027H01L2224/45139H01L2224/78301H01L24/46H01L24/16H01L2924/01078H01L29/0657H01L2924/01015H01L2224/81192H01L2924/01013H01L24/48H01L24/85H01L24/12H01L2924/30105H01L2924/10253H01L2924/01082H01L2224/85214H01L2924/01023H01L2924/01028H01L2224/48799H01L2224/81201H01L2224/45014H01L2924/10329H01L2924/01029H01L2224/45111H01L2224/48699H01L24/81
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Quick Facts
Patent No.
US 8,889,482
App. No.
12/484,221
Granted
Nov 18, 2014
Kind
B2
Abstract

The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The present process can fabricate multiple components separately before assembling them into a complete integrated circuit. In an aspect, the ready-for-assembling components are taken directly from processed wafers without any additional assembling processes, and/or having lateral dimensions less than 1 mm.

Claims (31)

1. A method for fabricating an integrated circuit, the method comprising:

separating the integrated circuit into multiple functional components; and

fabricating the multiple functional components on separate substrates so that the functional components are not in contact with each other when the fabrication is completed,

wherein each functional component has bond pads for connection with other functional component, and

wherein at least one functional component, when ready for assembling into a complete integrated circuit, has a lateral dimension less than 0.5 mm and a thickness less than 100 microns.

2. A method as in claim 1 further comprising:

assembling the multiple functional components into the complete integrated circuit, wherein the assembling comprises placement of the at least one functional component which is performed using a photosensitive thermally decomposable polymer.

3. A method as in claim 1 wherein the integrated circuit comprises a radio frequency identification (RFID) circuit.

4. A method as in claim 1 wherein the at least one component has a lateral dimension less than 0.1 mm.

5. A method as in claim 1 wherein the components are assembled close than 100 microns from each other.

6. A method for fabricating a radio frequency identification (RFID) tag circuit, the method comprising:

separating the RFID tag circuit into a digital logic component, a memory component and a RF component; and

fabricating the multiple components separately on separate substrates so that the components are not in contact with each other when the fabrication is completed, wherein each component has bond pads for connection with other component, and wherein at least one component, when ready for assembling into a complete RFID tag circuit, has a lateral dimension less than 1 mm and a thickness less than 100 microns.

7. A method as in claim 6 further comprising:

assembling the multiple components into the complete RFID tag circuit, wherein the assembling comprises placement of the at least one component which is performed using a photosensitive thermally decomposable polymer.

8. A method as in claim 7 wherein assembling the multiple components comprises placing one functional component face down on top of another functional component so that the bond pads in the one functional component line up with the bond pads in the another functional component.

9. A method as in claim 6 further comprising placing the multiple components in an at least partially stacked configuration.

10. A method as in claim 6 further comprising placing the multiple components in an at least partially coplanar configuration.

11. A method as in claim 6 wherein the at least one component has a lateral dimension less than 0.5 mm.

12. A method as in claim 6 wherein the at least one component has a lateral dimension less than 0.1 mm.

13. A method as in claim 6 wherein the components are assembled close than 100 microns from each other.

14. A method for fabricating an integrated circuit comprising multiple functional components, the method comprising:

fabricating the multiple functional components separately on separate substrates so that the functional components are not in contact with each other, wherein each functional component has bond pads for connection with other functional component, and wherein at least one functional component has a lateral dimension less than 0.5 mm and a thickness less than 100 microns;

transfer printing the at least one functional component with a decomposable adhesive; and

assembling the multiple functional components into the complete integrated circuit.

15. A method for fabricating a radio frequency identification (RFID) tag circuit comprising a digital logic component, a memory component and a RF component, the method comprising:

fabricating the digital logic component, the memory component and the RF component separately on separate substrates so that the components are not in contact with each other, wherein each component has bond pads for connection with other component, and wherein at least one component, when ready for assembling into a complete RFID tag circuit, has a lateral dimension less than 0.5 mm and a thickness less than 100 microns;

transfer printing the at least one component with a decomposable adhesive; and

assembling the digital logic component, the memory component and the RF component into the complete RFID tag circuit.

16. A method as in claim 15 wherein the at least one component is the digital logic component.

17. A method as in claim 15 wherein assembling the components comprises placing one component face down on top of another component so that the bond pads in the one component line up with the bond pads in the another component.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2020
From: TEREPAC CORPORATION
To: TERECIRCUITS CORPORATION
Reel/Frame 054084/0334 →
RELEASE OF SECURITY INTEREST Recorded Nov 27, 2019
From: WESTERN ONTARIO COMMUNTY FUTURE DEVELOPMENT CORPORATION ASSOCIATION
To: TEREPAC CORPORATION
Reel/Frame 051132/0225 →
SECURITY INTEREST Recorded Nov 6, 2014
From: TEREPAC CORPORATION
To: WESTERN ONTARIO COMMUNITY FUTURES DEVELOPMENT CORPORATION ASSOCIATION
Reel/Frame 034120/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2009
From: SHEATS, JAYNA
To: TEREPAC CORPORATION
Reel/Frame 022822/0476 →
Continuity (1)
Related Publication 20100314751A1 · Dec 16, 2010