Voltage level shift circuit and semiconductor integrated circuit
View Patent ↗Provided is a voltage level shift circuit including: a first voltage level shift circuit formed of a P-channel enhancement type transistor (M 1 ) and an N-channel depletion type MOS transistor (M 3 ); and a second voltage level shift circuit formed of a P-channel enhancement type transistor (M 2 ) and an N-channel depletion type MOS transistor (M 4 ). In the voltage level shift circuit, a cascode circuit using an N-channel depletion type transistor (M 5 ) is serially connected to the first voltage level shift circuit, a cascode circuit using an N-channel depletion type transistor (M 6 ) is serially connected to the second voltage level shift circuit, and a unit for complementarily controlling bias voltages of the respective cascode circuits. As a result, an output signal of the voltage level shift circuit connected to an input of a differential amplifier circuit, for expanding an input voltage range of a signal, is not affected by fluctuations in power supply voltage.
1. A voltage level shift circuit, comprising:
a first source follower circuit including:
a first P-channel enhancement type MOS transistor (M 21 ), a gate terminal of which is connected to a first voltage signal input terminal (In 11 ) and a drain terminal of which is grounded; and
a second P-channel enhancement type MOS transistor (M 22 ), a drain terminal of which is connected to a source terminal of the first P-channel enhancement type MOS transistor (M 21 ) and to a first voltage signal output terminal (Out 11 ) to be a constant current load;
a second source follower circuit including:
a third P-channel enhancement type MOS transistor (M 23 ), a gate terminal of which is connected to a second voltage signal input terminal (In 12 ) and a drain terminal of which is grounded; and
a fourth P-channel enhancement type MOS transistor (M 24 ), a drain terminal of which is connected to a source terminal of the third P-channel enhancement type MOS transistor (M 23 ) and to a second voltage signal output terminal (Out 12 ) to be a constant current load;
a cascode circuit formed of an N-channel depletion type MOS transistor (M 26 ), a gate terminal of which is connected to a fixed potential, a source terminal of which is connected to a source terminal of the second P-channel enhancement type MOS transistor (M 22 ) and to a source terminal of the fourth P-channel enhancement type MOS transistor (M 24 ), and a drain terminal of which is fixed to power supply voltage; and
a fifth P-channel enhancement type MOS transistor (M 25 ) which, together with the second P-channel enhancement type MOS transistor (M 22 ) and the fourth P-channel enhancement type MOS transistor (M 24 ), forms a current mirror circuit, for causing a current which is the same as a reference current (Iref) to flow through the second P-channel enhancement type MOS transistor (M 22 ) and the fourth P-channel enhancement type MOS transistor (M 24 ).
2. A semiconductor integrated circuit, comprising the voltage level shift circuit according to claim 1 .