Method for assuring counterbore depth of vias on printed circuit boards and printed circuit boards made accordingly
View Patent ↗A method is disclosed for fabricating a PCB so that is can easily be determined if a via in the PCB has not been counterbored to a desired depth. A PCB fabricated according to the method also is disclosed.
1. A method of determining a depth to which a via in a printed circuit board (PCB) has been counterbored, the via intended to carry signals between a first conductive layer and a second conductive layer of the PCB, comprising:
fabricating a structure in a third conductive layer of the PCB that couples the via electromagnetically to a first node on the PCB, the structure positioned so that the electromagnetic coupling to the first node will be disrupted if the via is counterbored through the third conductive layer;
counterboring the via; and
testing for the electromagnetic coupling between the first node and the via;
wherein the structure that is fabricated in the third conductive layer of the PCB that couples the via electromagnetically to the first node on the PCB comprises a trace that spans a portion of an anti-pad, and wherein at least a portion of the trace is removed when the via is counterbored through the third conductive layer.
2. The method of claim 1 wherein the electromagnetic coupling is a conductive connection.
3. The method of claim 2 wherein the testing comprises testing for electrical continuity between the via and the first node.
4. The method of claim 2 wherein fabricating the structure comprises fabricating a pad surrounding the via and a conductive trace between the pad and the first node.
5. The method of claim 2 wherein the first node is a ground node of the PCB.
6. The method of claim 2 wherein the third conductive layer is an adjacent conductive layer to the second conductive layer.
7. The method of claim 2 wherein the third conductive layer is a non-adjacent conductive layer to either the first conductive layer or the second conductive layer.
8. The method of claim 2 wherein the third conductive layer has a purpose in the PCB other than supporting the structure.
9. The method of claim 2 wherein the structure connects the via to another via in the PCB.
10. The method of claim 2 wherein the PCB comprises first and second vias and the structure comprises a conductive trace between the first and second vias and the testing comprises testing electrical continuity between the first and second vias.
11. The method of claim 1 wherein the via is an edge connector for an external device.
12. The method of claim 1 wherein the via is an edge connector for a plug-in card.
13. The method of claim 1 further comprising: testing for electromagnetic coupling of the via to the second conductive layer.
14. The method of claim 13 wherein the testing of electromagnetic coupling of the via to the second conductive layer comprises testing for conductive continuity of the via with a second node on the second layer.
15. A method of testing a printed circuit board (PCB) to assure that a via in the PCB has been counterbored to a desired depth, the via intended to carry signals between a first conductive layer and a first node on a second conductive layer of the PCB, comprising:
fabricating a structure in a third conductive layer of the PCB that provides a conductive connection of the via to a second node on the PCB, the structure positioned so that the conductive connection of the via to the second node will be disrupted if the via is counterbored through the third conductive layer;
counterboring the via;
after counterboring, testing for conductivity between the first node and the via;
after counterboring, testing for conductivity between the second node and the via; and
rejecting the PCB if either (a) there is no conductivity between the via and the first node or (b) there is conductivity between the via and the second node;
wherein the structure that is fabricated in the third conductive layer of the PCB that couples the via electromagnetically to the second node on the PCB comprises a trace that spans a portion of an anti-pad, and wherein at least a portion of the trace is removed when the via is counterbored through the third conductive layer.
16. The method of claim 15 wherein fabricating the structure comprises fabricating a pad surrounding the via and a conductive trace between the pad and the second node.
17. The method of claim 15 wherein the second node is a ground node of the PCB.
18. The method of claim 15 wherein the PCB comprises first and second vias and wherein the fabricating the structure comprises fabricating a conductive trace between the first and second vias and wherein the testing comprises testing electrical continuity between the first and second vias.
19. The method of claim 15 wherein the via is an edge connector for an external device.
20. A method of fabricating a printed circuit board (PCB) so as to permit determination of whether a via in the PCB has been counterbored to at least a minimum depth, comprising:
fabricating a PCB comprising at least a first conductive layer, a second conductive layer, and a third conductive layer, wherein the third conductive layer is not between the first conductive layer and the second conductive layer;
fabricating a conductive via extending through the PCB, the via intended to carry signals between a first node on the first conductive layer and a second node on the second conductive layer of the PCB;
fabricating a structure in the third conductive layer of the PCB that provides electromagnetic coupling of the via to a third node on the PCB, the structure positioned so that the electromagnetic coupling of the via to the third node will be disrupted if the via is counterbored through the third conductive layer;
counterboring the via;
wherein the structure that is fabricated in the third conductive layer of the PCB that provides electromagnetic coupling of the via to the third node on the PCB comprises a trace that spans a portion of an anti-pad, and wherein at least a portion of the trace is removed when the via is counterbored through the third conductive layer.
21. The method of claim 20 further comprising:
after counterboring, testing for conductivity between the first node and second node through the via;
after counterboring, testing for electromagnetic coupling between the third node and the via; and
rejecting the PCB if either (a) there is no conductivity between the via and the first node or (b) there is conductivity between the via and the third node.
22. The method of claim 20 wherein the electromagnetic coupling is a conductive connection.
23. The method of claim 22 wherein fabricating the structure comprises fabricating a pad surrounding the via and a conductive trace between the pad and the third node.
24. A printed circuit board (PCB) comprising:
a first conductive layer;
a second conductive layer;
a third conductive layer, the third conductive layer comprising a ground plane, the third conductive layer not between the first conductive layer and the second conductive layer;
a via extending through the PCB, the via intended to carry signals between a first node on the first conductive layer and a second node on the second conductive layer; and
a structure in the third conductive layer of the PCB that conductively connects the via to the ground plane, the structure positioned so that the conductive connection of the via to the ground plane will be disrupted if the via is counterbored through the third conductive layer;
wherein the structure in the third conductive layer of the PCB that conductively connects the via to the ground plane comprises a trace that spans a portion of an anti-pad, and wherein at least a portion of the trace is removed when the via is counterbored through the third conductive layer.
25. The PCB of claim 24 wherein the structure comprises a pad surrounding the via and a conductive trace between the pad and the ground plane.
26. The PCB of claim 24 wherein the third conductive layer is an adjacent conductive layer to the second conductive layer.
27. The PCB of claim 24 wherein the PCB comprises first and second vias and the structure comprises a conductive trace between the first and second vias and the testing comprises testing electrical continuity between the first and second vias.
28. The PCB of claim 24 wherein the via is an edge connector for an external device.
29. A printed circuit board (PCB) comprising:
a first conductive layer;
a second conductive layer;
a third conductive layer not between the first conductive layer and the second conductive layer;
a via extending through the PCB, the via intended to carry signals between a first node on the first conductive layer and a second node on the second conductive layer, the via comprising a non-conductive, counterbored portion and a conductive, non-counterbored portion, the counterbored portion extending into the third conductive layer; and
a conductive structure in the third conductive layer in conductive contact with a third node and in physical contact with the counterbored portion of the via;
wherein the conductive structure in the third conductive layer that is in conductive contact with the third node and in physical contact with the counterbored portion of the via comprises a trace that spans a portion of an anti-pad, and wherein at least a portion of the trace is removed when the via is counterbored through the third conductive layer.