Semiconductor integrated circuit device and manufacturing method thereof
View Patent ↗After silicon oxide film ( 9 ) is formed on the surface of a semiconductor substrate ( 1 ), the silicon oxide film ( 9 ) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film ( 10 ) is formed on the semiconductor substrate ( 1 ). Consequently, two kinds of gate insulation films, namely, a gate insulation film ( 12 ) comprised of stacked film of high dielectric constant insulation film ( 10 ) and silicon oxide film ( 9 ) and gate insulation film ( 11 ) comprised of the high dielectric constant insulation film ( 10 ) are formed on the semiconductor substrate ( 1 ).
1. A semiconductor integrated circuit device comprising:
a first MISFET for use as a selecting MISFET of a dynamic random access memory cell and formed in a first region of a semiconductor substrate; and
a second MISFET formed in a second region of the semiconductor substrate,
wherein the first MISFET includes:
a first insulation film formed over the first region;
a first portion of a third insulation film formed over the first insulation film;
a first gate electrode of the first MISFET formed over the first portion of the third insulation film,
wherein the second MISFET includes:
a second insulation film formed over the second region;
a second portion of the third insulation film formed over the second insulation film;
a second gate electrode of the second MISFET formed over the second portion of the third insulation film,
wherein the first and second portions of the third insulation film of the first and second MISFETs, respectively, are formed as a same layer,
wherein the first and second insulation films include silicon, oxygen, and nitrogen,
wherein the first and second portions of the third insulation film of the first and second MISFETs, respectively, have a greater dielectric constant than each of the first and second insulation films,
wherein a thickness of the first insulation film is larger than a thickness of the second insulation film, and
wherein thicknesses of the first and second portions of the third insulation film of the first and second MISFETs, respectively, are larger than the thicknesses of the first insulation film and the second insulation film, respectively.
2. A semiconductor integrated circuit device according to claim 1 , wherein the first insulation film is a silicon oxynitride film.
3. A semiconductor integrated circuit device according to claim 1 , wherein the second insulation film is a silicon oxynitride film.
4. A semiconductor integrated circuit device according to claim 1 , wherein the third insulation film is a hafnium oxide film.
5. A semiconductor integrated circuit device according to claim 1 , wherein the first and second MISFETs further comprise:
impurity extension regions of a first conductivity type formed in the semiconductor substrate on both sides of the first and second gate electrodes in the first and the second regions, respectively;
sidewalls formed over both sides of the first and second gate electrodes; and
impurity diffusion regions of the first conductivity type formed in the semiconductor substrate on both sides of the sidewalls in the first and the second regions.
6. A semiconductor integrated circuit device according to claim 5 , wherein the first and second MISFETs further comprise:
silicide layers formed over the first gate electrode, the second gate electrode, and the impurity diffusion regions.
7. A semiconductor integrated circuit device according to claim 6 , wherein the silicide layers include cobalt.
8. A semiconductor integrated circuit device according to claim 5 , wherein the first and second MISFETs further comprise:
halo layers of a second conductivity type formed in the semiconductor substrate on both sides of the first and second gate electrodes in the first and the second regions, respectively.
9. A semiconductor integrated circuit device according to claim 8 ,
wherein the first conductivity type is p-type; and
wherein the second conductivity type is n-type.
10. A semiconductor integrated circuit device according to claim 8 ,
wherein the first conductivity type is n-type; and
wherein the second conductivity type is p-type.
11. A semiconductor integrated circuit device comprising:
a first MISFET for use as a selecting MISFET of a dynamic random access memory cell and formed in a first region of a semiconductor substrate;
a second MISFET formed in a second region of the semiconductor substrate; and
a third MISFET formed in a third region of the semiconductor substrate,
wherein the first MISFET includes:
a first portion of a first insulation film formed over the first region;
a first portion of a third insulation film formed over the first portion of the first insulation film of the first MISFET;
a first gate electrode formed over the first portion of the third insulation film of the first MISFET;
wherein the second MISFET includes:
a second insulation film formed over the second region;
a second portion of the third insulation film formed over the second insulation film;
a second gate electrode formed over the second portion of the third insulation film of the second MISFET;
wherein the third MISFET includes:
a second portion of the first insulation film formed over the first region;
a third portion of the third insulation film formed over the second portion of the first insulation film of the third MISFET;
a third gate electrode formed over the third portion of the third insulation film of the third MISFET,
wherein the first, second, and third portions of the third insulation film of the first, second, and third MISFETs, respectively, are formed as a same layer,
wherein the first and second insulation films include silicon, oxygen, and nitrogen;
wherein the first, second, and third portions of the third insulation film of the first, second, and third MISFETs, respectively, have a greater dielectric constant than each of the first and second insulation films,
wherein thicknesses of the first and second portions of the first insulation film of the first and third MISFETs, respectively, are larger than a thickness of the second insulation film, and
wherein thicknesses of the first, second, and third portions of the third insulation film of the first, second, and third MISFETs, respectively, are larger than the thicknesses of the first and second portions of the first insulation film and the thickness of the second insulation film.
12. A semiconductor integrated circuit device according to claim 11 , wherein the first insulation film is a silicon oxynitride film.
13. A semiconductor integrated circuit device according to claim 11 , wherein the second insulation film is a silicon oxynitride film.
14. A semiconductor integrated circuit device according to claim 11 , wherein the third insulation film is a hafnium oxide film.
15. A semiconductor integrated circuit device according to claim 11 , wherein the first, second, and third MISFETs further comprise:
impurity extension regions of a first conductivity type formed in the semiconductor substrate on both sides of the first, second, and third gate electrodes in the first and the second regions;
sidewalls formed over both sides of the first, second, and third gate electrodes, and
impurity diffusion regions of the first conductivity type formed in the semiconductor substrate on both sides of the sidewalls in the first and the second regions.
16. A semiconductor integrated circuit device according to claim 15 , wherein the first, second, and third MISFETs further comprise:
silicide layers formed over the first gate electrode, the second gate electrode, the third gate electrode, and the impurity diffusion regions.
17. A semiconductor integrated circuit device according to claim 16 , wherein the silicide layers include cobalt.
18. A semiconductor integrated circuit device according to claim 15 , wherein the first, second, and third MISFETs further comprise:
halo layers of a second conductivity type formed in the semiconductor substrate.
19. A semiconductor integrated circuit device according to claim 18 ,
wherein the first conductivity type is p-type, and
wherein the second conductivity type is n-type.
20. Semiconductor integrated circuit device according to claim 18 ,
wherein the first conductivity type is n-type, and
wherein the second conductivity type is p-type.