Capacitor in semiconductor device and method of manufacturing the same
View Patent ↗A capacitor may include at least one of a polysilicon layer over a semiconductor substrate; a capacitor dielectric layer over a polysilicon layer; an insulating layer over a capacitor dielectric layer; a metal layer connected to a capacitor dielectric layer through a first region of an insulating layer; an upper metal wiring layer connected to a metal layer over an insulating layer; and/or a lower metal wiring line layer connected to a polysilicon layer through a metal contact that passes through a second region of an insulating layer and a capacitor dielectric layer over the insulating layer.
1. A capacitor comprising:
a polysilicon layer formed over a semiconductor substrate;
a capacitor dielectric layer formed over the polysilicon layer;
a gate insulating layer formed over the semiconductor substrate and under the polysilicon layer;
a metal layer formed over the capacitor dielectric layer; and
a sidewall spacer formed on a side of the polysilicon layer and on a top surface of the gate insulating layer, wherein the sidewall spacer is formed under the capacitor dielectric layer.
2. The capacitor of claim 1 , comprising an insulating layer formed over the capacitor dielectric layer, wherein:
a first contact hole is formed in the insulating layer; and
the metal layer is formed in the first contact hole.
3. The capacitor of claim 2 , wherein:
a second contact hole is formed through the insulating layer and the capacitor dielectric layer; and
a metal contact is formed in the second contact hole.
4. The capacitor of claim 3 , wherein the first contact hole and the second contact hole are formed in different regions of the insulating layer.
5. The capacitor of claim 3 , comprising:
an upper metal wiring layer formed over the metal layer; and
a lower metal wiring line layer formed over the metal contact.
6. The capacitor of claim 1 , wherein the polysilicon layer is a lower electrode of a capacitor.
7. The capacitor of claim 1 , wherein the metal layer is an upper electrode of a capacitor.
8. The capacitor of claim 1 , wherein the formation of the polysilicon layer includes N-type ion implantation.
9. The capacitor of claim 1 , wherein the width of the metal layer is larger than the width of the metal contact.
10. The capacitor of claim 1 , wherein the sidewall is in direct contact with the gate insulating layer, the polysilicon layer, and the capacitor dielectric layer.