Communication unit with analog test unit

1. An apparatus, comprising:

a device on a single integrated circuit, wherein the device includes:

an analog external interface;

a digital external interface;

a communication unit configured to perform communication via the analog external interface, wherein the communication unit has a transmitter portion and a receiver portion; and

an analog test unit including a tone generator unit, wherein the analog test unit is configured to test the transmitter and receiver portions of the communication unit by:

generating, with the tone generator unit, a test signal that is output by the transmitter portion and looped back to the receiver portion, wherein the generated test signal has an amplitude and a frequency that are specified by an external test unit; and

subsequently receiving the looped back test signal from the receiver portion;

wherein the analog test unit is configured to perform an analysis of the received looped back test signal and to communicate information regarding the analysis to the external test unit via the digital external interface.

2. The apparatus of claim 1 , wherein the transmitter portion includes a plurality of transmitter chains, and wherein the receiver portion includes a plurality of receiver chains, and wherein the analog test unit is configured to test at least two of the plurality of transmitter chains in parallel, and wherein the analog test unit is configured to test at least two of the plurality of receiver chains in parallel.

3. The apparatus of claim 1 , wherein the analog test unit includes a unit that is configured to:

correlate the received looped back test signal with a complex sinusoid; and

measure the power of the correlated signal.

4. The apparatus of claim 1 , wherein the analog test unit includes a complex multiply accumulate (CMAC) unit that is configured to measure the power of an I and/or Q quadrature channel of the received looped back test signal.

5. The apparatus of claim 1 , wherein the analog test unit is further configured to identify nonlinearity of a digital to analog converter (DAC) in the transmitter portion, and wherein the analog test unit is further configured to identify nonlinearity of an analog to digital converter (ADC) in the receiver portion.

6. The apparatus of claim 1 , wherein the analog test unit is further configured to perform analysis on a second test signal generated by the external test unit and received by the receiver portion; and

communicate information regarding the analysis of the second test signal to the external test unit via the digital external interface.

7. The apparatus of claim 1 , wherein the analog test unit is further configured to generate a second test signal and transmit the second test signal to the external test unit through the transmitter portion and the analog external interface.

8. The apparatus of claim 1 , further comprising the external test unit, wherein the external test unit includes a load board that includes circuitry that is configured to loop back the test signal that is output by the transmitter portion to the receiver portion.

9. A method, comprising:

a test device sending, in parallel, a common set of one or more instructions to each of a plurality of integrated circuits under test by the test device, wherein each of the plurality of integrated circuits includes a communication unit that has an analog portion, and wherein each of the plurality of integrated circuits further includes an analog test unit, wherein sending the common set of instructions to each of the plurality of integrated circuits causes the analog test unit in each of the integrated circuits to:

test the analog portion of its respective communication unit, by generating a respective test signal with a tone generator unit included in that analog test unit, wherein the common set of instructions specifies an amplitude and a frequency of the generated test signals;

store corresponding test results in a memory of the integrated circuit;

the test device receiving, in parallel, the corresponding test results from each of the plurality of integrated circuits, wherein the corresponding test results are received via a digital interface of each of the plurality of integrated circuits.