Controlling pit formation in a III-nitride device
View Patent ↗A device includes a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region and a plurality of layer pairs disposed within one of the n-type region and the p-type region. Each layer pair includes an InGaN layer and pit-filling layer in direct contact with the InGaN layer. The pit-filling layer may fill in pits formed in the InGaN layer.
1. A device comprising:
a semiconductor structure comprising:
a III-nitride light emitting layer disposed between an n-type region and a p-type region, wherein the n-type region comprises an InGaN contact layer; and
a plurality of layer pairs disposed within one of the n-type region and the p-type region, each layer pair comprising:
an InGaN layer; and
a pit-filling layer in direct contact with the InGaN layer, wherein the pit filling layer is one of GaN, AlGaN, AlInGaN, and AlInN; and
a metal contact disposed on a portion of the InGaN contact layer.
2. The device of claim 1 wherein each pit-filling layer is GaN.
3. The device of claim 1 wherein each pit-filling layer is AlGaN.
4. The device of claim 3 wherein each pit-filling layer has an AlN composition between 3% and 10%.
5. The device of claim 1 wherein each pit-filling layer is AlInGaN.
6. The device of claim 5 wherein each pit-filling layer has an AlN composition between 3% and 10%.
7. The device of claim 1 wherein each InGaN layer has an InN composition between 3% and 10%.
8. The device of claim 1 wherein each InGaN layer has a thickness between 100 and 500 nm.
9. The device of claim 1 wherein each pit-filling layer has a thickness between 10 and 50 nm.
10. The device of claim 1 further comprising a plurality of pits disposed on a top surface of the InGaN layer in one of the layer pairs, wherein a size of the plurality of pits on the top surface of the InGaN layer is greater than a size of a plurality of pits disposed on a top surface of the pit-filling layer in the same layer pair.
11. The device of claim 1 wherein between 2 and 50 layer pairs are included in the semiconductor structure.
12. The device of claim 1 wherein portions of the light emitting layer and p-type region are removed to expose portions of the n-type region and the metal contact is a first metal contact disposed on the exposed portions of the n-type region, the device further comprising:
a second metal contact disposed on the p-type region;
wherein the first metal contact and the second metal contact are disposed on a same side of the semiconductor structure.
13. The device of claim 1 wherein each pit-filling layer is a substantially single crystal layer.