Method and apparatus for system testing using multiple processors
View Patent ↗An apparatus is provided for performing testing of at least a portion of a system under test via a Test Access Port (TAP) configured to access the system under test. The apparatus includes a first processor for executing instructions adapted for controlling testing of at least a portion of the system under test via the TAP, and a second processor for supporting an interface to the TAP. The first processor is configured for detecting, during execution of the test instructions, TAP-related instructions associated with control of the TAP, and propagating the TAP-related instructions toward the second processor. The second processor is configured for receiving the TAP-related instructions detected by the first processor and processing the TAP-related instructions. The first processor is configured for performing at least one task contemporaneously with processing of the TAP-related instructions by the second processor. An associated method also is provided.
1. An apparatus for performing testing of at least a portion of a system under test via a Test Access Port (TAP) configured to access the system under test, comprising:
a first processor configured to:
execute a set of instructions configured to control testing of at least a portion of the system under test via the TAP, the set of instructions comprising a TAP-related instruction associated with control of the TAP, the TAP-related instruction comprising an opcode supported by a second processor, the second processor configured to support an interface to the TAP and configured to process the TAP-related instruction for generating one or more TAP control signals adapted to control at least one scan operation via the TAP;
detect the TAP-related instruction during execution of the set of instructions; and
propagate the TAP-related instruction toward the second processor.
2. The apparatus of claim 1 , wherein the first processor is a central processor unit resident on a board and the second processor is a test co-processor unit resident on the board.
3. The apparatus of claim 1 , further comprising a main memory and a persistent memory storage.
4. The apparatus of claim 3 , further comprising:
a main processor interface bus;
wherein the first processor, the second processor, the main memory, and the persistent memory storage each are communicatively connected to the main processor interface bus.
5. The apparatus of claim 1 , further comprising:
an auxiliary processor interface configured to couple the first processor and the second processor.
6. The apparatus of claim 5 , wherein the first processor is configured to propagate the TAP-related instruction toward the second processor via the auxiliary processor interface.
7. The apparatus of claim 1 , wherein the first processor is configured to detect and propagate the TAP-related instruction as an instruction exception.
8. The apparatus of claim 1 , wherein the first processor comprises a cache memory.
9. The apparatus of claim 1 , wherein the second processor comprises a scatter/gather direct memory access (DMA) unit.
10. The apparatus of claim 9 , wherein the first processor is configured to configure at least one scatter/gather DMA table of the scatter/gather DMA unit prior to detecting the TAP-related instruction.
11. The apparatus of claim 9 , wherein the first processor is configured to configure at least one scatter/gather DMA table of the scatter/gather DMA unit via at least one of:
a main processor interface bus; or
an auxiliary processor interface connecting the first processor and the second processor.
12. The apparatus of claim 1 , wherein the first processor is configured to share physical memory space with the second processor using arbitrated access.
13. The apparatus of claim 1 , wherein the second processor is configured to support a set of instructions supporting access to and control of the TAP.
14. The apparatus of claim 1 , wherein the first processor is a central processor unit and the second processor is a test adjunct processor unit.
15. The apparatus of claim 14 , wherein the central processor unit and the test adjunct processor unit reside on different boards.
16. The apparatus of claim 1 , further comprising a main memory and a persistent memory associated with the first processor.
17. The apparatus of claim 16 , further comprising:
a main processor interface bus;
wherein the first processor, the main memory, and the persistent memory each are coupled to the main processor interface bus.
18. The apparatus of claim 1 , further comprising a local test memory associated with the second processor.
19. The apparatus of claim 18 , further comprising:
an internal interface bus;
wherein the second processor and the local test memory each are coupled to the internal interface bus.
20. The apparatus of claim 1 , further comprising:
a first input/output module associated with the first processor; and
a second input/output module associated with the second processor;
wherein the first input/output module and the second input/output module are configured to support a communications interface between the first processor and the second processor.
21. The apparatus of claim 20 , wherein the first processor and the first input/output module each are coupled to a main processor interface bus.
22. The apparatus of claim 20 , wherein the communications interface is a Serializer-Deserializer (SERDES) interface.
23. The apparatus of claim 22 , wherein the first input/output module and the second input/output module are SERDES modules.
24. The apparatus of claim 1 , wherein the first processor is configured to:
packetize the TAP-related instruction: and
propagate the packetized TAP-related instruction toward the second processor via a communications interface.
25. The apparatus of claim 1 , wherein the first processor has a main memory associated therewith and the second processor has a local test memory associated therewith, wherein the TAP-related instruction comprises at least one extension command configured for performing block memory copies between the main memory and the local test memory.
26. A method for performing testing of at least a portion of a system under test accessible via a Test Access Port (TAP), the method comprising:
executing, by a first processor, a set of instructions configured to control testing of at least a portion of the system under test via the TAP, the set of instructions comprising a TAP-related instruction associated with control of the TAP, the TAP-related instruction comprising an opcode supported by a second processor, the second processor configured to support an interface to the TAP and configured to process the TAP-related instruction for generating one or more TAP control signals adapted to control at least one scan operation via the TAP;
detecting, by the first processor during execution of the set of instructions, the TAP-related instruction associated with control of the TAP; and
propagating the TAP-related instruction from the first processor toward the second processor.
27. The apparatus of claim 1 , wherein the first processor is configured to perform at least one task contemporaneously with processing of the TAP-related instruction by the second processor.
28. The apparatus of claim 1 , further comprising:
the second processor.
29. The apparatus of claim 28 , wherein the second processor is configured to support a set of instructions supporting access to and control of the TAP.
30. The apparatus of claim 28 , wherein the first processor is a central processor unit and the second processor is a test adjunct processor unit.
31. The apparatus of claim 30 , wherein the central processor unit and the test adjunct processor unit reside on the same board.
32. A non-transitory computer-readable storage medium storing instructions which, when executed by a computer, cause the computer to perform a method for performing testing of at least a portion of a system under test accessible via a Test Access Port (TAP), the method comprising:
executing, by a first processor, a set of instructions configured to control testing of at least a portion of the system under test via the TAP, the set of instructions comprising a TAP-related instruction associated with control of the TAP, the TAP-related instruction comprising an opcode supported by a second processor, the second processor configured to support an interface to the TAP and configured to process the TAP-related instruction for generating one or more TAP control signals adapted to control at least one scan operation via the TAP;
detecting, by the first processor during execution of the set of instructions, the TAP-related instruction associated with control of the TAP; and
propagating the TAP-related instruction from the first processor toward the second processor.