Thin film transistor array panel and method for manufacturing the same
View Patent ↗A thin film transistor array panel according to the present invention includes: an insulation substrate having a display area and a peripheral area; a plurality of thin film transistors disposed in the display area; a plurality of gate lines connected to the thin film transistors; a plurality of data lines connected to the thin film transistors; a driving unit disposed in the peripheral area of the insulation substrate, and controlling the thin film transistor; a plurality of signal lines connecting between the driving unit and the gate lines or the data lines; and a dummy pattern overlapping the signal line and made of a transparent conductive material.
1. A method for manufacturing a thin film transistor array panel, comprising:
forming a gate line and a first signal line to connect the gate line to a driving circuit on a substrate;
forming a semiconductor on the gate line;
forming a data line and a drain electrode on the semiconductor;
forming a second signal line to connect the data line to the driving circuit;
forming a passivation layer and a sacrificial layer on the data line, the drain electrode, the first signal line, and the second signal line;
forming a photosensitive film pattern comprising a first portion and a second portion of different thicknesses on the sacrificial layer;
etching the sacrificial layer and the passivation layer using the photosensitive film pattern as a mask to form a contact hole exposing the drain electrode;
removing the exposed sacrificial layer after removing the first portion of the photosensitive film pattern, and forming an undercut under the second portion of the photosensitive film pattern;
forming a transparent conductive layer on the second portion of the photosensitive film pattern, the exposed drain electrode, and the passivation layer; and
removing the second portion of the photosensitive film pattern disposed under the transparent conductive layer thereby removing the transparent conductive layer disposed on the second portion of the photosensitive film pattern among the transparent conductive layer to form a pixel electrode and a dummy pattern.
2. The method of claim 1 , wherein the photosensitive film pattern is formed using a semi-transparent layer.
3. The method of claim 1 , wherein the first portion of the photosensitive film pattern corresponds to the pixel electrode, the first signal line, and the second signal line, and the second portion of the photosensitive film pattern corresponds to the portion between first signal lines, and between second signal lines and on the gate line and the data line.
4. The method of claim 1 , wherein the undercut is formed with a depth of 0.2-0.3 μm.
5. The method of claim 1 , wherein the forming of the semiconductor and the forming of the data line and the drain electrode are performed using another photosensitive film pattern comprising two portions with different thicknesses.
6. The method of claim 1 , wherein the sacrificial layer comprises silicon nitride.