Thin film transistor array and method of manufacturing the same
View Patent ↗A method of manufacturing a thin film transistor array substrate includes: forming a gate pattern on a substrate; forming a first gate insulating film and a second gate insulating film on the substrate; forming a source/drain pattern and a semiconductor pattern on the substrate; forming a passivation film on the substrate; forming a photo-resist pattern on the passivation film; patterning the passivation film using the photo-resist pattern to form a passivation film pattern, the patterning of the passivation film including over-etching the passivation film to form an open region in the passivation film; forming a transparent electrode film on the substrate; removing the photo-resist pattern and a portion of the transparent electrode film on the photo-resist pattern; and forming a pixel electrode on the first gate insulating layer.
1. A substrate for a display panel, the substrate comprising:
a base substrate;
a gate line disposed in a first direction on the base substrate, the gate line including a gate electrode;
a first gate insulating layer disposed on the gate line;
a second gate insulating layer disposed on the first gate insulating layer;
a semiconductor layer disposed on the second gate insulating layer, the semiconductor layer including a channel portion;
a data line disposed in a second direction, substantially perpendicular to the first direction, on the semiconductor layer, the data line including a source electrode and a drain electrode disposed opposite to the source electrode;
a passivation layer disposed on the gate line and the data line, the passivation layer including an opening through which a portion of the first gate insulating layer and a portion of the drain electrode are exposed; and
a pixel electrode disposed on the first gate insulating layer in the opening and connected to the drain electrode.
2. The substrate of claim 1 , wherein a planar shape defined by the pixel electrode is substantially the same as a planar shape defined by the opening.
3. The substrate of claim 2 , further comprising a storage electrode disposed in the second direction on the base substrate, wherein the storage electrode is made of a substantially same material as the gate line.
4. The substrate of claim 3 , wherein a width of the storage electrode, measured in the first direction, is greater than a corresponding width of the data line measured in the first direction.
5. The substrate of claim 4 , wherein the first gate insulating layer comprises silicon oxide.
6. The substrate of claim 5 , wherein the second gate insulating layer comprises silicon nitride.
7. The substrate of claim 2 , wherein the first gate insulating layer comprises silicon oxide.
8. The substrate of claim 7 , wherein the second gate insulating layer comprises silicon nitride.
9. The substrate of claim 1 , further comprising a storage electrode disposed in the second direction on the base substrate, wherein the storage electrode is made of a substantially same material as the gate line.
10. The substrate of claim 9 , wherein a width of the storage electrode, measured in the first direction, is greater than a corresponding width of the data line measured in the first direction.
11. The substrate of claim 9 , wherein the first gate insulating layer comprises silicon oxide.
12. The substrate of claim 11 , wherein the second gate insulating layer comprises silicon nitride.
13. The substrate of claim 1 , wherein the first gate insulating layer comprises silicon oxide.
14. The substrate of claim 13 , wherein the second gate insulating layer comprises silicon nitride.