Bit labeling for amplitude phase shift constellation used with low density parity check (LDPC) codes
An approach is provided for bit labeling of a signal constellation. A transmitter generates encoded signals using, according to one embodiment, a structured parity check matrix of a Low Density Parity Check (LDPC) code. The transmitter includes an encoder for transforming an input message into a codeword represented by a plurality of set of bits. The transmitter includes logic for mapping non-sequentially (e.g., interleaving) one set of bits into a higher order constellation (Quadrature Phase Shift Keying (QPSK), 8-PSK, 16-APSK (Amplitude Phase Shift Keying), 32-APSK, etc.), wherein a symbol of the higher order constellation corresponding to the one set of bits is output based on the mapping.
1. A method, performed by an apparatus of a receiver, comprising:
receiving an encoded signal representing a binary Low Density Parity Check (LDPC) codeword that has a parity check matrix with a structure that provides contiguous storage of edge values for decoding of the encoded signal,
wherein the encoded signal has been modulated using bit mapping into a constellation corresponding to one of an 8-Phase Shift Keying (PSK) modulation scheme, a 16-APSK (Amplitude Phase Shift Keying) modulation scheme, or a 32-APSK modulation scheme.
2. A method according to claim 1 , wherein the constellation of the 8-PSK modulation scheme follows a Gray-coded scheme and has adjacent clockwise symbols representing bits, respectively, in the following sequence, 000, 001, 101, 111, 011, 010, 110, and 100.
3. A method according to claim 1 , wherein the constellation corresponds to the 16-APSK modulation scheme and includes two concentric rings of uniformly spaced 4 and 12 PSK points,
wherein a first one of the concentric rings provides adjacent clockwise symbols representing bits, respectively, in the following sequence, 1100, 1101, and 1111, 1110; and
wherein a second one of the concentric rings provides adjacent clockwise symbols representing bits, respectively, in the following sequence, 0000, 0100, 0101, 0001, 1001, 1011, 0011, 0111, 0110, 0010, 1010, and 1000.
4. A method according to claim 1 , wherein the constellation corresponds to the 32-APSK modulation scheme and includes three concentric rings of uniformly spaced 4, 12 and 16 PSK points,
wherein a first one of the concentric rings provides adjacent clockwise symbols representing bits, respectively, in the following sequence, 10001, 10011, 10111, and 10101;
wherein a second one of the concentric rings provides adjacent clockwise symbols representing bits, respectively, in the following sequence, 00000, 10000, 10010, 00010, 00011, 00111, 00110, 10110, 10100, 00100, 00101, and 00001; and
wherein a third one of the concentric rings provides adjacent clockwise symbols representing bits, respectively, in the following sequence, 11001, 01000, 11000, 11010, 01010, 11011, 01011, 01111, 11111, 01110, 11110, 11100, 01100, 11101, 01101, and 01001.
5. A method according to claim 1 , wherein the constellation corresponds to the 8-PSK modulation scheme, the method further comprising:
determining an i th 8-PSK symbol based on the set of (N/3+i) th , (2N/3+i) th and i th LDPC encoded bits, wherein i=0, 1, 2, . . . , N/3−1, and N is the coded LDPC block size.
6. A method according to claim 1 , wherein the constellation corresponds to the 16-APSK modulation scheme, the method further comprising:
determining an i th 16-APSK symbol based on the set of (N/2+2i) th , 2i th , (N/2+2i+1) th and (2i+1) th LDPC encoded bits, wherein i=0, 1, 2, . . . , N/3−1, and N is the coded LDPC block size.
7. A method according to claim 1 , wherein the constellation corresponds to the 32-APSK modulation scheme, the method further comprising:
determining an i th 32-APSK symbol based on the set of (N/5+i) th , (2N/5+i) th , (4N/5+i) th , (3N/5+i) th and i th LDPC encoded bits, wherein i=0, 1, 2, . . . , N/5−1, and N is the coded LDPC block size.
8. A chipset configured in a receiver, comprising:
logic configured to receive an encoded signal representing a binary Low Density Parity Check (LDPC) codeword that has a parity check matrix with a structure that provides contiguous storage of edge values for decoding of the encoded signal,
wherein the encoded signal has been modulated using bit mapping into a constellation corresponding to one of an 8-Phase Shift Keying (PSK) modulation scheme, a 16-APSK (Amplitude Phase Shift Keying) modulation scheme, or a 32-APSK modulation scheme.
9. A chipset according to claim 8 , wherein the constellation of the 8-PSK modulation scheme follows a Gray-coded scheme and has adjacent clockwise symbols representing bits, respectively, in the following sequence, 000, 001, 101, 111, 011, 010, 110, and 100.
10. A chipset according to claim 8 , wherein the constellation corresponds to the 16-APSK modulation scheme and includes two concentric rings of uniformly spaced 4 and 12 PSK points,
wherein a first one of the concentric rings provides adjacent clockwise symbols representing bits, respectively, in the following sequence, 1100, 1101, and 1111, 1110; and
wherein a second one of the concentric rings provides adjacent clockwise symbols representing bits, respectively, in the following sequence, 0000, 0100, 0101, 0001, 1001, 1011, 0011, 0111, 0110, 0010, 1010, and 1000.
11. A chipset according to claim 8 , wherein the constellation corresponds to the 32-APSK modulation scheme and includes three concentric rings of uniformly spaced 4, 12 and 16 PSK points,
wherein a first one of the concentric rings provides adjacent clockwise symbols representing bits, respectively, in the following sequence, 10001, 10011, 10111, and 10101;
wherein a second one of the concentric rings provides adjacent clockwise symbols representing bits, respectively, in the following sequence, 00000, 10000, 10010, 00010, 00011, 00111, 00110, 10110, 10100, 00100, 00101, and 00001; and
wherein a third one of the concentric rings provides adjacent clockwise symbols representing bits, respectively, in the following sequence, 11001, 01000, 11000, 11010, 01010, 11011, 01011, 01111, 11111, 01110, 11110, 11100, 01100, 11101, 01101, and 01001.
12. A chipset according to claim 8 , wherein the constellation corresponds to the 8-PSK modulation scheme, the logic being further configured to:
determine an i th 8-PSK symbol based on the set of (N/3+i) th , (2N/3+i) th and i th a LDPC encoded bits, wherein i=0, 1, 2, . . . , N/3−1, and N is the coded LDPC block size.
13. A chipset according to claim 8 , wherein the constellation corresponds to the 16-APSK modulation scheme, the logic being further configured to:
determine an i th 16-APSK symbol based on the set of (N/2+2i) th , 2i th , (N/2+2i+1) th and (2i+1) th LDPC encoded bits, wherein 1=0, 1, 2, . . . , N/3−1, and N is the coded LDPC block size.
14. A chipset according to claim 8 , wherein the constellation corresponds to the 32-APSK modulation scheme, the logic being further configured to:
determine an i th 32-APSK symbol based on the set of (N/5+i) th , (2N/5+i) th , (4N/5+i) th , (3N/5+i) th and i th LDPC encoded bits, wherein i=0, 1, 2, . . . , N/5−1, and N is the coded LDPC block size.
15. A receiver comprising:
a processor configured to receive an encoded signal representing a binary Low Density Parity Check (LDPC) codeword that has a parity check matrix with a structure that provides contiguous storage of edge values for decoding of the encoded signal,
wherein the encoded signal has been modulated using bit mapping into a constellation corresponding to one of an 8-Phase Shift Keying (PSK) modulation scheme, a 16-APSK (Amplitude Phase Shift Keying) modulation scheme, or a 32-APSK modulation scheme.
16. A receiver according to claim 15 , wherein the constellation of the 8-PSK modulation scheme follows a Gray-coded scheme and has adjacent clockwise symbols representing bits, respectively, in the following sequence, 000, 001, 101, 111, 011, 010, 110; and 100.
17. A receiver according to claim 15 , wherein the constellation corresponds to the 16-APSK modulation scheme and includes two concentric rings of uniformly spaced 4 and 12 PSK points,
wherein a first one of the concentric rings provides adjacent clockwise symbols representing bits, respectively, in the following sequence, 1100, 1101, and 1111, 1110, and
wherein a second one of the concentric rings provides adjacent clockwise symbols representing bits, respectively, in the following sequence, 0000, 0100, 0101, 0001, 1001, 1011, 0011, 0111, 0110, 0010, 1010, and 1000.
18. A receiver according to claim 15 , wherein the constellation corresponds to the 32-APSK modulation scheme and includes three concentric rings of uniformly spaced 4, 12 and 16 PSK points,
wherein a first one of the concentric rings provides adjacent clockwise symbols representing bits, respectively, in the following sequence, 10001, 10011, 10111, and 10101;
wherein a second one of the concentric rings provides adjacent clockwise symbols representing bits, respectively, in the following sequence, 00000, 10000, 10010, 00010, 00011, 00111, 00110, 10110, 10100, 00100, 00101, and 00001; and
wherein a third one of the concentric rings provides adjacent clockwise symbols representing bits, respectively, in the following sequence, 11001, 01000, 11000, 11010, 01010, 11011, 01011, 01111, 11111, 01110, 11110, 11100, 01100, 11101, 01101, and 01001.
19. A receiver according to claim 15 , wherein the constellation corresponds to the 8-PSK modulation scheme, the processor being further configured to:
determine an i th 8-PSK symbol based on the set of (N/3+i) th , (2N/3+i) th and i th LDPC encoded bits, wherein i=0, 1, 2, . . . , N/3−1, and N is the coded LDPC block size.
20. A receiver according to claim 15 , wherein the constellation corresponds to the 16-APSK modulation scheme, the processor being further configured to:
determine an i th 16-APSK symbol based on the set of (N/2+2i) th , 2i th , (N/2+2i+1) th and (2i+1) th LDPC encoded bits, wherein i=0, 1, 2, . . . , N/3−1, and N is the coded LDPC block size.
21. A receiver according to claim 15 , wherein the constellation corresponds to the 32-APSK modulation scheme, the processor being further configured to:
determine an i th 32-APSK symbol based on the set of (N/5+i) th , (2N/5+i) th , (4N/5+i) th , (3N/5+i) th and i th LDPC encoded bits, wherein i=0, 1, 2, . . . , N/5−1, and N is the coded LDPC block size.
22. A method, performed by an apparatus, comprising:
receiving a set of encoded bits representing a binary Low Density Parity Check (LDPC) codeword that has a parity check matrix with a structure that provides contiguous storage of edge values for decoding of the LDPC codeword;
writing the set of encoded bits on a column by column basis into a memory; and
reading the encoded bits on a row by row basis from the memory for mapping to a signal constellation.
23. A method according to claim 22 , wherein the LDPC codeword utilizes an outer Bose Chaudhuri Hocquenghem (BCH) code.
24. A chipset comprising:
logic configured to receive a set of encoded bits representing a binary Low Density Parity Check (LDPC) codeword that has a parity check matrix with a structure that provides contiguous storage of edge values for decoding of the LDPC codeword; and
a read/write logic configured to write the set of encoded bits on a column by column basis and to read the encoded bits on a row by row basis for mapping to a signal constellation.
25. A chipset according to claim 24 , wherein the LDPC codeword utilizes an outer Bose Chaudhuri Hocquenghem (BCH) code.
26. A receiver comprising a chipset according to claim 24 .
27. A method for transmitting encoding signals, the method comprising:
receiving encoded bits of a codeword from a binary Low Density Parity Check (LDPC) encoder;
writing the encoded bits to a memory on a column by column basis; and
reading out the encoded bits from the memory on a row by row basis for mapping to a signal constellation.
28. An apparatus comprising:
a binary Low Density Parity Check (LDPC) encoder configured to transform an input message into a codeword represented by encoded bits; and
logic configured to write the encoded bits to a memory on a column by column basis, and read out the encoded bits from the memory on a row by row basis for mapping to a signal constellation.
29. An apparatus comprising:
a receiver configured to receive, demodulate, and decode bits of a codeword that are encoded by a binary Low Density Parity Check (LDPC) encoder, interleaved by an interleaver that wrote the bits into a memory on a column by column basis and read out the bits from the memory on a row by row basis, and mapped the bits read out from the memory to a signal constellation.
30. A method for transmitting encoding signals, the method comprising:
receiving encoded bits of a codeword from a binary Low Density Parity Check (LDPC) encoder;
writing the encoded bits to a block interleaver on a column by column basis;
reading out the encoded bits from the block interleaver on a row by row basis;
non-sequentially mapping, according to a structure of the codeword, the encoded bits read out from the block interleaver into a constellation corresponding to a modulation scheme; and
outputting a symbol of the constellation based on the mapping for transmission over a channel.
31. An apparatus comprising:
a binary Low Density Parity Check (LDPC) encoder configured to transform an input message into a codeword represented by encoded bits; and
logic configured to write the encoded bits to a block interleaver on a column by column basis, read out the encoded bits from the block interleaver on a row by row basis, to non-sequentially map, according to a structure of the codeword, the encoded bits read out from the block interleaver into a constellation corresponding to a modulation scheme, and output a symbol of the constellation based on the mapping for transmission over a channel.