High slew rate amplifier, analog-to-digital converter using same, CMOS imager using the analog-to-digital converter and related methods
View Patent ↗An amplifier, which may be used in a pipelined analog-to-digital converter, includes a first amplifier stage driving a second amplifier stage. At least one compensation capacitor is coupled to provide negative feedback through the capacitor from the second amplifier stage to the first amplifier stage. The slew rate of the amplifier is enhanced by substantially reducing the negative feedback coupled through the capacitor during a period following the transition of a signal applied to an input terminal of the amplifier. If the first stage of the amplifier has complementary signal nodes, the negative feedback coupled through the capacitor may be reduced, for example, by closing a switch coupled between first and second complementary nodes of the first amplifier stage.
1. An amplifier, comprising:
a first amplifier stage;
a second amplifier stage coupled to an output node of the first amplifier stage and an output node of the second amplifier stage coupled to the first amplifier stage to provide negative feedback to the first amplifier stage; and
a switch circuit coupled to one of the first and second amplifier stages and configured to reduce negative feedback for at least a portion of time when the amplifier is operating.
2. The amplifier of claim 1 wherein the second amplifier stage is capacitively coupled to the first amplifier stage to provide negative feedback.
3. The amplifier of claim 1 , further comprising compensation capacitors through which the second amplifier stage is coupled to the first amplifier stage to provide negative feedback.
4. The amplifier of claim 1 , further comprising compensation capacitors through which the output node of the second amplifier is coupled to complementary nodes of the first amplifier stage.
5. The amplifier of claim 1 wherein the switch circuit comprises a switch circuit configured to couple complementary nodes of the first amplifier stage.
6. The amplifier of claim 1 wherein the switch circuit comprises a switch circuit configured to couple complementary nodes of the first amplifier stage during an initial portion of an amplifying period of the amplifier.
7. The amplifier of claim 1 wherein the switch circuit comprises a switch circuit configured to couple complementary nodes of the first amplifier stage in response to activation of the amplifier.
8. The amplifier of claim 1 wherein the switch circuit comprises:
a pass gate coupled to complementary nodes of the first amplifier stage and configured to couple the same in response to an activation pulse; and
a pulse generator coupled to the pass gate and configured to generate the activation pulse in response to a rising transition of a clock signal.
9. The amplifier of claim 1 wherein the switch circuit comprises a switch circuit configured to couple the complementary nodes for a period of time sufficient to substantially reduce negative feedback.
10. A differential amplifier, comprising:
a first amplifier stage having first and second complementary input nodes, first and second complementary output nodes, and first and second complementary nodes intermediate the first and second input nodes and the first and second output nodes;
a second amplifier stage having first and second complementary input nodes coupled to the first and second complementary output nodes of the first amplifier stage, the second amplifier stage further having first and second complementary output nodes;
first and second feedback circuits coupled to respective complementary output nodes of the second amplifier stage and respective complementary nodes of the first amplifier stage; and
a switch circuit coupled to the first and second complementary nodes of the first amplifier stage and configured to couple the first and second complementary nodes to each other.
11. The differential amplifier of claim 10 wherein the switch circuit comprises a switch circuit configured to couple the first and second complementary nodes to each other in response to operation of the differential amplifier.
12. The differential amplifier of claim 10 wherein the switch circuit comprises a switch circuit configured to couple the first and second complementary nodes to each other during an initial portion of an amplifying period of the differential amplifier.
13. The differential amplifier of claim 10 wherein the first and second feedback circuits comprise capacitors.
14. A method of enhancing the slew rate of an amplifier having first and second amplifier stages and a compensating capacitor coupled to provide negative feedback through the capacitor from the second amplifier stage to the first amplifier stage, the method comprising at least substantially reducing the negative feedback coupled through the capacitor.
15. The method of claim 14 wherein the act of at least substantially reducing the negative feedback coupled through the capacitor comprises attenuating the negative feedback coupled through the capacitor.
16. The method of claim 14 wherein the act of at least substantially reducing the negative feedback coupled through the capacitor comprises coupling complementary nodes in the first amplifier stage to each other.
17. The method of claim 14 wherein the act of at least substantially reducing the negative feedback comprises at least substantially reducing the negative feedback coupled through the capacitor responsive to a transition of a clock signals that is received at the start of an amplifying period of the amplifier.
18. The method of claim 14 wherein the amplifier includes two compensating capacitors each of which is coupled to provide negative feedback through the capacitor from the second amplifier stage to the first amplifier stage, and wherein the act of at least substantially reducing the negative feedback coupled through the capacitor during an initial portion of an amplifying period of the amplifier comprises substantially reducing the negative feedback coupled through both of the capacitors during an initial portion of an amplifying period of the amplifier.
19. In a pipelined analog-to-digital converter in which an analog input signal is sequentially processed by a plurality of analog-to-digital converter stages each of which includes an amplifier having first and second amplifier stages coupled to provide negative feedback, a method of enhancing the performance of the analog-to-digital converter, comprising the method comprising at least substantially reducing the negative feedback during an initial portion of an amplifying period of the amplifier.
20. The method of claim 19 wherein the act of at least substantially reducing the negative feedback coupled through the capacitor comprises attenuating the negative feedback coupled through a compensating capacitor coupled between the first and second amplifier stages.
21. The method of claim 19 wherein the act of at least substantially reducing the negative feedback comprises coupling complementary nodes in the first amplifier stage to each other.
22. The method of claim 19 wherein the act of at least substantially reducing the negative feedback during an initial portion of an amplifying period of the amplifier comprises:
generating a clock signal having a transition occurring at the start of an amplifying period of the amplifier; and
substantially reducing the negative feedback responsive to the clock signal.
23. The method of claim 19 wherein the amplifier includes two compensating capacitors each of which is coupled to provide negative feedback through the capacitor from the second amplifier stage to the first amplifier stage, and wherein the act of at least substantially reducing the negative feedback during an initial portion of an amplifying period of the amplifier comprises substantially reducing the negative feedback coupled through both of the capacitors during an initial portion of an amplifying period of the amplifier.