IP Library Granted Patent US 8,179,250
Granted Patent B2
US 8,179,250 · App. 12/501,509 · Granted May 15, 2012

Power management interface

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Quick Facts
Patent No.
US 8,179,250
App. No.
12/501,509
Granted
May 15, 2012
Kind
B2
Abstract

A power management interface is provided and includes a switch, a transmitting circuit, and a receiving circuit. The switch is coupled to an AC power line for controlling a power line signal to a load. The transmitting circuit generates a switching signal to control the switch and achieve a phase modulation to the power line signal in response to a transmitting-data. The receiving circuit is coupled to receive the power line signal for detecting a phase of the power line signal and generating a receiving-data to control power of the load. The receiving-data is generated in accordance with the phase detection of the power line signal and correlated to the transmitting-data.

Claims (38)

1. A power management interface comprising:

a switch coupled to an AC power line for controlling a power line signal to a load;

a transmitting circuit generating a switching signal to control the switch and achieve a phase modulation to the power line signal in response to a transmitting-data; and

a receiving circuit coupled to receive the power line signal for detecting a phase of the power line signal and generating a receiving-data to control power of the load;

wherein the receiving-data is generated in accordance with the phase detection of the power line signal and correlated to the transmitting-data, and

wherein the transmitting circuit comprises:

an input circuit coupled to the AC power line for generating a clock signal;

a register memorizing a state of the transmitting-data for generating a state signal; and

an output circuit generating the switching signal coupled to control the switch in response to the state signal and the clock signal.

2. The power management interface as claimed in claim 1 , wherein the input circuit comprises:

a voltage divider coupled to the AC power line to generate an input signal;

a comparator generating a zero-crossing signal by comparing the input signal with a reference signal; and

a pulse generator generating the clock signal in response to the zero-crossing signal;

wherein the clock signal is coupled to the register.

3. The power management interface as claimed in claim 1 , wherein the receiving circuit comprises:

a detection circuit coupled to receive the power line signal and detect the phase of the power line signal for generating the receiving-data;

wherein the receiving-data is provided to the load.

4. The power management interface as claimed in claim 3 , wherein the detection circuit comprising:

a rectifier and an attenuator coupled to receive the power line signal for generating an attenuated signal;

a comparator coupled to receive attenuated signal for generating a data signal in response to a turned-on angle of the power line signal;

a pulse generator generating a pulse signal in response to the data signal, wherein the pulse signal indicates the available of the data signal; and

a flip-flop receiving the pulse signal and the data signal and sampling the data signal according to the pulse signal for generating the receiving-data.

5. The power management interface as claimed in claim 1 , wherein the receiving circuit comprises:

a detection circuit coupled to receive the power line signal and detecting the phase of the power line signal for generating the receiving-data; and

a control circuit generating a control signal according to the receiving-data;

wherein the control signal is provided to the load.

6. The power management interface as claimed in claim 5 , wherein the detection circuit comprises:

a rectifier and an attenuator coupled to receive the power line signal for generating an attenuated signal;

a comparator coupled to receive attenuated signal for generating a data signal in response to a turned-on angle of the power line signal;

a pulse generator generating a pulse signal in response to the data signal, wherein the pulse signal indicates the available of the data signal;

a flip-flop receiving the pulse signal and the data signal and sampling the data signal according to the pulse signal for generating the receiving-data.

7. The power management interface as claimed in claim 5 , wherein the control circuit is implemented by adigital-analog converter.

8. The power management interface as claimed in claim 1 , wherein the switch is a MOSFET or an IGBT.

9. A power management interface comprising:

a switch coupled to an AC power line for controlling a power line signal to a load;

a transmitting circuit generating a switching signal to control the switch and achieve a phase modulation to the power line signal in response to a transmitting-data; and

a receiving circuit coupled to receive the power line signal for detecting a phase of the power line signal and generating a receiving-data to control power of the load;

wherein the receiving-data is generated in accordance with the phase detection of the power line signal and correlated to the transmitting-data, wherein the phase modulation is achieved by controlling a turn-on angle of the power line signal.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RECORDED AT REEL 046410, FRAME 0933 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046410/0933 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2017
From: FAIRCHILD (TAIWAN) CORPORATION (FORMERLY SYSTEM GENERAL CORPORATION)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 042328/0318 →
CHANGE OF NAME Recorded May 3, 2016
From: SYSTEM GENERAL CORPORATION
To: FAIRCHILD (TAIWAN) CORPORATION
Reel/Frame 038599/0043 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2009
From: YANG, TA-YUNG; LIN, YI-CHI; WU, YUNG-SHENG; LU, WEN-CHANG; YANG, SHIH-JEN
To: SYSTEM GENERAL CORPORATION
Reel/Frame 022943/0566 →