Method and apparatus for preventing congestive placement

1. A method of preventing congestive placement, applied to a logic circuit layout comprising N input ends, 2 K logic circuits and M output ends, M and N being positive integers greater than 1 and K being a positive integer, the method comprising:

checking a hierarchy configuration of the logic circuit layout;

adding (N−K) buffers to each of the 2 K logic circuits;

adding a selection unit to the logic circuit layout; and

using a computer, synthesizing the logic circuit layout according to a plurality of don't touch synthesis commands associated with the added buffers.

2. The method of preventing congestive placement as claimed in claim 1 , wherein the (N−K) buffers access data according to access signals inputted at (N−K) input ends among the N input ends to generate M data signals.

3. The method of preventing congestive placement as claimed in claim 1 , wherein the selecting unit selects a corresponding logic circuit from the 2 K logic circuits according to K selection signals inputted at the K second input ends among the N input ends, and outputs the M data signals to the M output ends.

4. The method of preventing congestive placement as claimed in claim 1 , wherein the selecting unit is a multiplexer.

5. The method of preventing congestive placement as claimed in claim 1 , wherein in the synthesized logic circuit layout, each of the 2 K logic circuits is kept independent, and are not coupled to or merged with one another, or simplified.

6. The method of preventing congestive placement as claimed in claim 1 , further comprising:

realizing the synthesized logic circuit layout by implementing automatic placement-and-routing (APR).

7. The method of preventing congestive placement as claimed in claim 1 , wherein a value of (N−K) is smaller than or equal to 12.

8. The method of preventing congestive placement as claimed in claim 1 , wherein the synthesizing step synthesizes the logic circuit layout from an original register transfer level (RTL) hardware description language (HDL) to a gate level HDL.

9. The method of preventing congestive placement as claimed in claim 1 , wherein the logic layout circuit further comprises a look-up table.

10. An apparatus for preventing congestive placement, applied to a logic circuit layout comprising (N−K) first input ends, K second input ends, 2 K logic circuits and M output ends, M and N being positive integers greater than 1 and K being a positive integer, the apparatus comprising:

a restructuring module, coupled to the logic circuit layout, for restructuring the logic circuit layout to a restructured logic circuit layout by adding a selecting unit to the logic circuit layout and (N−K) buffers to each of the 2 K logic circuits; wherein the selecting unit is coupled to the K second input ends, the 2 K logic circuits and the M output ends, and the (N−K) buffers are coupled to the (N−K) first input ends; and

a synthesizing module, coupled to the logic circuit layout, for synthesizing the restructure logic circuit layout according to a plurality of don't touch synthesis commands associated with the added buffers.

11. The apparatus for preventing congestive placement as claimed in claim 10 , wherein the selecting unit is a multiplexer.

12. The apparatus for preventing congestive placement as claimed in claim 10 , wherein each of the 2 K logic circuits is kept independent, and is not coupled to or merged with one another, or simplified.

13. The apparatus for preventing congestive placement as claimed in claim 10 , further comprising:

an APR module, coupled to the logic circuit, for realizing the synthesized logic circuit layout by implementing APR.

14. The apparatus for preventing congestive placement as claimed in claim 10 , wherein a value of (N−K) is smaller than or equal to 12.

15. The apparatus for preventing congestive placement as claimed in claim 10 , wherein the synthesizing step synthesizes the logic circuit layout from an original RTL HDL to a gate level HDL.

16. The apparatus for preventing congestive placement as claimed in claim 10 , wherein the logic layout circuit further comprises a look-up table.

17. The apparatus for preventing congestive placement as claimed in claim 10 , wherein the logic circuit layout accesses data according to (N−K) access signals inputted at the (N−K) first input ends to generate M data signals.

18. The apparatus for preventing congestive placement as claimed in claim 17 , wherein selecting unit selects a corresponding logic circuit from the 2 K logic circuits according to K selection signals inputted at the K second input ends among the N input ends, and outputs the M data signal to the M output ends.

19. The apparatus for preventing congestive placement as claimed in claim 10 , further comprising:

a checking module, for checking a hierarchy configuration of the logic circuit layout.

20. The apparatus for preventing congestive placement as claimed in claim 10 , wherein the selecting unit comprises:

a plurality of first selectors, coupled to the 2 K logic circuits, for receiving data signals inputted at the 2 K logic circuits, and

a second selector, coupled to the plurality of first selectors, the K second input ends and the M output ends, for selecting a corresponding logic circuit from the 2 K logic circuits according to K selection signals inputted at the K second input ends among the N input ends, and outputting the M data signals to the M output ends.