Electrostatic discharge protection device, method of manufacturing the same, method of testing the same

1. A method of manufacturing an electrostatic protection device comprising:

forming a plurality of trenches over a semiconductor substrate at a predetermined depth, wherein the predetermined depth sequentially increases from a first region of the semiconductor substrate to a second region of the semiconductor substrate; and then

forming a plurality of device isolation regions in the semiconductor substrate by filling the trenches with an insulation layer material; and then

forming a plurality of gate electrodes spaced apart over the semiconductor substrate and between the adjacent device isolation regions; and then

forming a plurality of source regions and drain regions in the semiconductor substrate at both lateral sides of each one of the gate electrodes.

2. The method of claim 1 , wherein forming the plurality of trenches comprises:

forming a plurality of photoresist patterns spaced apart a predetermined lateral distance over the semiconductor substrate to define a device isolation region, wherein the predetermined lateral distance sequentially increases from the first region of the semiconductor substrate to the second region of the semiconductor substrate; and then

etching the plurality of trenches using the photoresist pattern as an etching mask; and then

removing the photoresist patterns.

3. The method of claim 2 , wherein the plurality of trenches are etched using a dry etching process.

4. The method of claim 3 , wherein the dry etching process comprises reactive ion etching.

5. The method of claim 1 , wherein the first region of the semiconductor substrate comprises a device formation region where a circuit device is to be connected to the electrostatic protection device and the second region of the semiconductor substrate comprises a ground region.

6. The method of claim 5 , wherein the plurality of device isolation regions comprises a first device isolation region formed immediately adjacent to the device formation region of the semiconductor substrate, a second device isolation region laterally spaced immediately adjacent to the first device isolation region, a third device isolation region laterally spaced immediately adjacent to the second device isolation region and a fourth device isolation region laterally spaced immediately adjacent to the third device isolation region and the ground region of the semiconductor substrate.

7. The method of claim 6 , wherein the plurality of device isolation regions comprises a first device isolation region formed immediately adjacent to the first region of the semiconductor substrate, a second device isolation region laterally spaced immediately adjacent to the first device isolation region, a third device isolation region laterally spaced immediately adjacent to the second device isolation region and a fourth device isolation region laterally spaced immediately adjacent to the third device isolation region and the second region of the semiconductor substrate.

8. The method of claim 1 , wherein forming the plurality of gate electrodes comprises:

sequentially forming an insulating layer and a polysilicon layer over the semiconductor substrate including device isolation regions; and then

etching the insulating layer and the polysilicon layer to expose the device isolation regions.

9. An electrostatic protection device comprising:

a semiconductor substrate having a first region and a second region;

a plurality of device isolation regions formed in the semiconductor substrate at a predetermined width and a predetermined depth, wherein the predetermined width and the predetermined depth sequentially increases from the first region of the semiconductor substrate to the second region of the semiconductor substrate;

a plurality of gate electrodes formed over the semiconductor substrate in spaces between adjacent ones of the device isolation regions; and

a plurality of source regions and drain regions formed in the semiconductor substrate at both lateral sides of the gate electrode.

10. The electrostatic protection device of claim 9 , wherein the first region of the semiconductor substrate comprises a device formation region where a circuit device is to be connected to the electrostatic protection device and the second region of the semiconductor substrate comprises a ground region.

11. The electrostatic protection device of claim 10 , wherein the plurality of device isolation regions comprises a first device isolation region formed immediately adjacent to the device formation region of the semiconductor substrate, a second device isolation region laterally spaced immediately adjacent to the first device isolation region, a third device isolation region laterally spaced immediately adjacent to the second device isolation region and a fourth device isolation region laterally spaced immediately adjacent to the third device isolation region and the ground region of the semiconductor substrate.

12. The electrostatic protection device of claim 9 , wherein the plurality of device isolation regions comprises a first device isolation region formed immediately adjacent to the first region of the semiconductor substrate, a second device isolation region laterally spaced immediately adjacent to the first device isolation region, a third device isolation region laterally spaced immediately adjacent to the second device isolation region and a fourth device isolation region laterally spaced immediately adjacent to the third device isolation region and the second region of the semiconductor substrate.

13. The electrostatic protection device of claim 9 , further comprising a plurality of gate insulating layers interposed between the gate electrodes and the semiconductor substrate.