Test device and a semiconductor integrated circuit device
A test device includes a semiconductor substrate having a first test region and a second test region defined thereon, wherein a layout of the first test region includes first active regions separated from each other by isolation regions in the semiconductor substrate, second active regions formed between the first active regions, first gate lines formed on the semiconductor substrate, wherein each of the first gate lines has a first end adjacent to one of the first active regions and a second end adjacent to an end of one of the second active regions, respectively, first shared contacts each formed over a respective one of the second ends of the first gate lines and an upper part of one of the first active regions, and first nodes formed on the first shared contacts to be electrically connected to the first shared contacts, respectively.
1. A semiconductor integrated circuit device, comprising:
a semiconductor substrate having a first region and a second region defined thereon;
a pair of first active regions formed in the first region, wherein the first active regions extend in a first direction in the semiconductor substrate and are separated from each other;
a pair of second active regions formed in the first region between the first active regions;
a pair of first active regions formed in the second region, wherein the first active regions extend in the first direction in the semiconductor substrate to correspond to the pair of first active regions in the first region;
a pair of second active regions formed in the second region to correspond to the pair of second active regions in the first region;
a pair of first gate lines extending in a second direction different from the first direction and separated from each other, wherein the first gate lines are included in one or both of the first and second regions, and wherein each of the first gate lines has a first end adjacent to one of the first active regions in the region in which it is formed and a second end adjacent to an end of one of the second active regions in the region in which it is formed, respectively;
a pair of first shared contacts formed in the first region, wherein each contact is partially formed over a respective one of the second ends of the first gate lines in the first region and a top surface of one of the second active regions in the first region;
a pair of second shared contacts formed in the second region to correspond to the pair of first shared contacts;
a pair of first nodes formed in the first region that apply voltages to the pair of first shared contacts, respectively; and
a pair of second nodes formed in the second region to correspond to the pair of first nodes, wherein the second nodes apply voltages to the pair of the second shared contacts, respectively.
2. The semiconductor integrated circuit device of claim 1 , further comprising a first current detection part formed in the first region that determines whether current flows between the pair of first nodes.
3. The semiconductor integrated circuit device of claim 1 , further comprising a second current detection part formed in the second region that determines whether current flows between the pair of second nodes.
4. The semiconductor integrated circuit device of claim 1 , wherein leakage current caused by at least one of the first gate lines is measured by determining whether current flows between the pair of first nodes and between the pair of second nodes.
5. The semiconductor integrated circuit device of claim 1 , wherein the first region comprises a first test region and the second region comprises a second test region.
6. The semiconductor integrated circuit device of claim 5 , further comprising a static memory cell region defined on the semiconductor substrate, wherein the first active regions, the first gate lines, the first shared contacts and the first nodes, which are formed in the first region, have the same layouts as those of the static memory cell region.
7. The semiconductor integrated circuit device of claim 5 , wherein an interlayer insulating layer is filled in an area of the second region that corresponds to the first gate lines in the first region.
8. The semiconductor integrated circuit device of claim 1 , wherein the first region comprises a static memory cell region and the second region comprises a test region.