IP Library Granted Patent US 7,989,925
Granted Patent B2
US 7,989,925 · App. 12/502,940 · Granted Aug 2, 2011

Method for forming a group III nitride material on a silicon substrate

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Quick Facts
Patent No.
US 7,989,925
App. No.
12/502,940
Granted
Aug 2, 2011
Kind
B2
Abstract

Semiconductor process technology and devices are provided, including a method for forming a high quality group III nitride layer on a silicon substrate and to a device obtainable therefrom. According to the method, a pre-dosing step is applied to a silicon substrate, wherein the substrate is exposed to at least 0.01 μmol/cm 2 of one or more organometallic compounds containing Al, in a flow of less than 5 μmol/min. The preferred embodiments are equally related to the semiconductor structure obtained by the method, and to a device comprising said structure.

Claims (21)

1. A semiconductor structure comprising:

a silicon substrate;

an intermediate layer on the silicon substrate, the intermediate layer comprising at least one area consisting of a silicon carbide layer throughout a thickness of the area, the area having a thickness of 2 nm or less; and

a group III nitride layer on the intermediate layer, wherein the group III nitride layer or the silicon carbide layer has a value of full width at half maximum lower than about 1000 arc sec.

2. The structure according to claim 1 , wherein said intermediate layer is a silicon carbide layer.

3. The structure according to claim 1 , wherein the silicon carbide area has a thickness of 1 nm or less.

4. The structure according to claim 1 , wherein the silicon carbide area is an atomic monolayer of silicon carbide.

5. A semiconductor structure comprising:

a silicon substrate;

an intermediate layer on the silicon substrate, the intermediate layer comprising at least one area consisting of a silicon carbide layer throughout a thickness of the area, the area having a thickness of 2 nm or less; and

a group III nitride layer on the intermediate layer, wherein the group III nitride is selected from the group consisting of AlN, GaN, AlGaN, InGaN, and AlInGaN, and wherein the group III nitride layer or the silicon carbide layer has a value of full width at half maximum lower than about 1000 arc sec.

6. A semiconductor structure comprising:

a silicon substrate;

an intermediate layer on the silicon substrate, the intermediate layer comprising at least one area consisting of a silicon carbide layer throughout a thickness of the area the area having a thickness of 2 nm or less;

a group III nitride layer on the intermediate layer, wherein the group III nitride layer or the silicon carbide layer has a value of full width at half maximum lower than about 1000 arc sec; and

a further group III nitride layer on the group III nitride layer.

7. The structure according to claim 6 , wherein the further group III nitride is selected from the group consisting of AlN, GaN, AlGaN, InGaN, and AlInGaN.

8. The structure according to claim 1 , wherein the group III nitride layer has a film thickness of less than 10 μm.

9. A semiconductor device comprising the semiconductor structure according to claim 1 .

10. A semiconductor device comprising the semiconductor structure according to claim 5 .

11. A semiconductor device comprising the semiconductor structure according to claim 6 .

Assignments (2)
"IMEC" IS AN ALTERNATIVE OFFICIAL NAME FOR "INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW" Recorded Apr 7, 2010
From: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW
To: IMEC
Reel/Frame 024200/0675 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2009
From: CHENG, KAI; LEYS, MAARTEN; DEGROOTE, STEFAN
To: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC); KATHOLIEKE UNIVERSITEIT LEUVEN (KUL)
Reel/Frame 022997/0155 →