Semiconductor memory device and manufacturing method thereof
View Patent ↗A semiconductor memory device includes: a semiconductor substrate; a first impurity region; a second impurity region; a channel region; a first gate formed on a main surface on a side of the first impurity region; a second gate formed on the main surface on a side of the second impurity region, with a second insulating film being interposed; and a third insulating film formed on a side surface of the first gate. An interface between the third insulating film and the semiconductor substrate directly under the third insulating film is located above an interface between the second insulating film and the main surface of the semiconductor substrate directly under the second insulating film. The total number of steps can thus be reduced, and lower cost is achieved.
1. A semiconductor memory device comprising:
a semiconductor substrate;
an isolation region selectively formed on a main surface of said semiconductor substrate;
an active region defined by said isolation region on said main surface of said semiconductor substrate;
a first impurity region formed on said active region, capable of serving as a source region;
a second impurity region formed on said active region, capable of serving as a drain region;
a channel region formed on said main surface of said semiconductor substrate between said first impurity region and said second impurity region;
a control gate electrode formed annularly in plan view on an upper surface of said channel region on a side of said second impurity region, with a first insulating film being interposed;
a recessed portion formed on a side surface of said control gate electrode located on a side of said first impurity region;
a sidewall-shaped memory gate electrode formed annularly in plan view on the upper surface of said channel region on a side of said first impurity region, with a second insulating film capable of accumulating charges being interposed, as well as on one side surface of said control gate electrode;
a connection portion connected to said memory gate electrode and formed in said recessed portion; and
a voltage application portion connected to said connection portion, capable of applying a voltage to said memory gate electrode.