IP Library Granted Patent US 8,187,696
Granted Patent B2
US 8,187,696 · App. 12/504,996 · Granted May 29, 2012

Circuit materials, circuits laminates, and method of manufacture thereof

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Quick Facts
Patent No.
US 8,187,696
App. No.
12/504,996
Granted
May 29, 2012
Kind
B2
Abstract

A circuit substrate laminate, comprising a conductive metal layer; and a dielectric composite material having a dielectric constant of less than about 3.5 and a dissipation factor of less than about 0.006, wherein the dielectric composite material comprises: a polymer resin; and about 10 to about 70 volume percent of cenospheres having a ferric oxide content of less than or equal to 3 weight percent.

Claims (32)

1. A circuit subassembly, comprising

a conductive layer disposed on a dielectric substrate layer, wherein the dielectric layer comprises, based on the volume of the dielectric layer,

about 30 to about 90 volume percent of a polymer matrix material, and

about 10 to about 70 volume percent of a filler component comprising a plurality of cenospheres having a ferric oxide content of about 3 weight percent or less based on the weight of the cenospheres;

wherein the circuit laminate has a dielectric constant of less than about 3.5 and a dissipation factor of less than about 0.006.

2. The circuit subassembly of claim 1 , wherein the cenospheres have a median particle diameter of 20 to 100 micrometers.

3. The circuit subassembly of claim 1 , wherein the filler component comprises 1 to 100 volume percent of the cenospheres, based on the total volume of the filler component.

4. The circuit subassembly of claim 1 , wherein the filler component comprises an additional filler, in an amount from 20 to 80 vol. %, based on the total volume of the filler component.

5. The circuit subassembly of claim 4 , wherein the additional filler is silica, fused amorphous silica, or a combination thereof.

6. The circuit subassembly of claim 4 , wherein the additional filler is alumina trihydrate, magnesium hydroxide, or a combination thereof.

7. The circuit subassembly of claim 1 , wherein the polymer matrix material comprises 1,2-polybutadiene, polyisoprene, polyetherimide, fluoropolymer, polyphenylene ether, polyimide, polyetheretherketone, polyamidimide, polyethylene terephthalate, polyethylene naphthalate, polycyclohexylene terephthalate, or combinations thereof.

8. The circuit subassembly of claim 1 , wherein the polymer matrix material is polytetrafluoroethylene.

9. The circuit subassembly of claim 1 , wherein the polymer matrix material is 1,2-polybutadiene, polyisoprene, or a combination of 1,2-polybutadiene and polyisoprene.

10. The circuit subassembly of claim 1 , wherein the polymer matrix material comprises a poly(arylene ether).

11. The circuit subassembly of claim 10 , wherein the poly(arylene ether) is carboxy-functionalized.

12. The circuit subassembly of claim 10 , further comprising a polybutadiene or polyisoprene polymer.

13. The circuit subassembly of claim 12 , wherein the polybutadiene or polyisoprene polymer is carboxy-functionalized, and comprises butadiene, isoprene, or butadiene and isoprene, and less than 50 weight percent of a co-curable monomer.

14. The circuit subassembly of claim 1 , further comprising a second conductive layer disposed on a side of the dielectric substrate layer opposite the conductive layer.

15. The circuit subassembly of claim 1 , wherein the conductive layer is a copper foil.

16. The circuit subassembly of claim 1 , wherein the conductive layer is etched to provide a circuit.

17. The circuit subassembly of claim 1 , wherein the conductive layer is in contact with the dielectric layer.

18. The circuit subassembly of claim 1 , wherein a bond ply is disposed between and in contact with the conductive layer and the dielectric substrate layer.

19. A circuit comprising the circuit subassembly of claim 1 .

20. A multi-layer circuit comprising circuit subassembly of claim 1 .

21. A method of making a circuit subassembly, the method comprising:

combining a polymer matrix material and a filler component to form a dielectric composite material;

forming a layer of the dielectric composite material, wherein the dielectric composite material comprises about 30 to about 90 volume percent of a polymer matrix material, and about 10 to about 70 volume percent of a filler component comprising a plurality of cenospheres having a ferric oxide content of about 3 weight percent or less based on the weight of the cenospheres;

disposing a conductive layer on the dielectric composite layer; and

laminating the dielectric composite layer and the conductive layer to form a circuit subassembly having a dielectric constant of less than about 3.5 and a dissipation factor of less than about 0.006.

22. The method of claim 21 , wherein the cenospheres have a median particle diameter of 20 to 100 micrometers.

23. The method of claim 21 , wherein the filler component comprises an additional filler, in an amount from 20 to 80 vol. %, based on the total volume of the filler component, wherein the additional filler is silica, fused amorphous silica, alumina trihydrate, magnesium hydroxide, or a combination thereof.

24. A circuit subassembly made by the method of claim 21 .

Assignments (4)
SECURITY INTEREST Recorded Feb 20, 2017
From: WORLD PROPERTIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041757/0778 →
SECURITY INTEREST Recorded Jun 26, 2015
From: WORLD PROPERTIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 036021/0047 →
SECURITY AGREEMENT Recorded Dec 2, 2010
From: WORLD PROPERTIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 025438/0024 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2009
From: PAUL, SANKAR K.; CAISSE, CHRISTOPHER J.; BAARS, DIRK M.; HORN, ALLEN F., III
To: WORLD PROPERTIES, INC.
Reel/Frame 023200/0502 →