Semiconductor device comprising capacitive elements
View Patent ↗A technology capable of reducing the fraction defective of a MOS capacitor without the need to perform a screening is provided. A MOS capacitor MOS 1 and a MOS capacitor MOS 2 are coupled in series between a high potential and a low potential to form a series capacitive element. Then, a polysilicon capacitor PIP 1 and a polysilicon capacitor PIP 2 are coupled in parallel with the series capacitive element. Specifically, a high-concentration semiconductor region HS 1 constituting a lower electrode of the MOS capacitor MOS 1 and a high-concentration semiconductor region HS 2 constituting a lower electrode of the MOS capacitor MOS 2 are coupled. Further, an electrode E 1 constituting an upper electrode of the MOS capacitor MOS 1 is coupled to the low potential (for example, GND) and an electrode E 3 constituting an upper electrode of the MOS capacitor MOS 2 is coupled to the high potential (for example, power source potential).
1. A semiconductor device having a first capacitance formation region and a second capacitance formation region in a semiconductor substrate, the semiconductor device comprising:
a first capacitive element including: (a1) a first lower electrode having a first semiconductor region formed in the semiconductor substrate; (a2) a first capacitor insulating film formed over the first semiconductor region; and (a3) a first upper electrode having a first conductive film formed over the first capacitor insulating film; and
a second capacitive element including: (b1) a second lower electrode having the first conductive film; (b2) a second capacitor insulating film formed over the first conductive film; and (b3) a second upper electrode having a second conductive film formed over the second capacitor insulating film,
formed in the first capacitance formation region, and
a third capacitive element including: (c1) a third lower electrode having a second semiconductor region formed in the semiconductor substrate; (c2) a third capacitor insulating film formed over the second semiconductor region; and (c3) a third upper electrode having a first conductive film formed over the first capacitor insulating film, and
a fourth capacitive element including: (d1) a fourth lower electrode having the first conductive film; (d2) a fourth capacitor insulating film formed over the first conductive film; and (d3) a fourth upper electrode having a second conductive film formed over the second capacitor insulating film,
formed in the second capacitance formation region,
wherein the first capacitive element and the third capacitive element are coupled in series to form a series capacitive element;
wherein the series capacitive element and the second capacitive element are coupled in parallel; and
wherein the series capacitive element and the fourth capacitive element are also coupled in parallel.
2. The semiconductor device according to claim 1 ,
wherein the first semiconductor region and the second semiconductor region are a semiconductor region of the same conductivity type,
wherein the first semiconductor region has the highest impurity concentration among semiconductor regions existing in the semiconductor substrate in the first capacitance formation region, and
wherein the second semiconductor region has the highest impurity concentration among semiconductor regions existing in the semiconductor substrate in the second capacitance formation region.
3. The semiconductor device according to claim 2 ,
wherein the first semiconductor region and the second semiconductor region are an n-type semiconductor region with the same concentration.
4. The semiconductor device according to claim 1 ,
wherein all of the series capacitive element formed by coupling in series the first capacitive element and the third capacitive element, the second capacitive element coupled in parallel with the series capacitive element, and the fourth capacitive element coupled in parallel with the series capacitive element are coupled between a first potential and a second potential lower than the first potential.
5. The semiconductor device according to claim 4 , further having in the semiconductor substrate:
a low withstand voltage MISFET formation region in which a low withstand voltage MISFET operating using a first power source potential is formed; and
a high withstand voltage MISFET formation region in which a high withstand voltage MISFET operating using a second power source potential higher than the first power source potential is formed.
6. The semiconductor device according to claim 5 ,
wherein the series capacitive element, the second capacitive element, and the fourth capacitive element are used in a circuit that uses the low withstand voltage MISFET.
7. The semiconductor device according to claim 6 ,
wherein the first potential is the first power source potential that operates the low withstand voltage MISFET and the second potential is a reference potential.
8. The semiconductor device according to claim 1 ,
wherein the semiconductor substrate further has a memory cell formation region in which a nonvolatile memory cell is formed,
wherein the nonvolatile memory cell includes: (e1) a gate insulating film formed on the semiconductor substrate; (e2) a control gate electrode formed on the gate insulating film; and (e3) a memory gate electrode formed on one of sidewalls of the control gate electrode via an insulating film, and
wherein the insulating film includes a first potential barrier film, a charge storage film formed over the first potential barrier film, and a second potential barrier film formed over the charge storage film.
9. The semiconductor device according to claim 8 ,
wherein the gate insulating film, the first capacitor insulating film, and the third capacitor insulating film are formed from the same film,
wherein the control gate electrode is formed by processing the first conductive film,
wherein the insulating film, the second capacitor insulating film, and the fourth capacitor insulating film are formed from the same film, and
wherein the memory gate electrode is formed by processing the second conductive film.
10. The semiconductor device according to claim 9 ,
wherein the first conductive film and the second conductive film are formed from a polysilicon film.
11. The semiconductor device according to claim 10 ,
wherein the insulating film and the second capacitor insulating film are formed from a laminated film including a first silicon oxide film, a silicon nitride film, and a second silicon oxide film.
12. The semiconductor device according to claim 1 ,
wherein the first semiconductor region is an n-type well and the second semiconductor region is a p-type well.
13. The semiconductor device according to claim 12 ,
wherein all of the series capacitive element formed by coupling in series the first capacitive element and the third capacitive element, the second capacitive element coupled in parallel with the series capacitive element, and the fourth capacitive element coupled in parallel with the series capacitive element are coupled between a first potential and a second potential lower than the first potential.
14. The semiconductor device according to claim 13 ,
wherein, among the series capacitive elements coupled between the first potential and the second potential, the first capacitive element is arranged on the first potential side and the third capacitive element is arranged on the second potential side.
15. The semiconductor device according to claim 14 ,
wherein the first upper electrode of the first capacitive element is coupled to the first potential and the third upper electrode of the third capacitive element is coupled to the second potential.
16. The semiconductor device according to claim 15 ,
wherein the first potential is a power source potential and the second potential is a reference potential.