Semiconductor device and semiconductor substrate having selectively etched portions filled with silicon germanium
View Patent ↗In order to provide a semiconductor device having a field effect transistor with a low power consumption and a high speed by use of the combination of Si and an element such as Ge, C or the like of the same group as Si, a strain is applied by a strain applying semiconductor layer 2 to a channel forming layer I having a channel of the field effect transistor formed therein so that the mobility of carriers in the channel is made larger than the mobility of carriers in that material of the channel forming layer which is unstrained.
1. A semiconductor device, comprising:
a silicon substrate;
a p-type MISFET having a first source region, a first drain region and a first channel region which is arranged between the first source region and the first drain region; and
an n-type MISFET having a second source region, a second drain region and a second channel region which is arranged between the second source region and the second drain region,
wherein the silicon substrate is selectively etched,
wherein at least one said selectively etched portion is filled up with an SiGe layer,
wherein the first drain region and the second source region are formed in the SiGe layers, respectively,
wherein a silicon film is formed on a top surface of the SiGe layer,
wherein the first channel region and the second channel region are formed in the silicon substrate and are disposed on a sidewall of the SiGe layer, respectively,
wherein a compressive stress is applied to the first channel region to increase a drain current of the p-type MISFET, and
wherein a tensile stress is applied to the second channel region in order to increase a drain current of the n-type MISFET.
2. A semiconductor device according to the claim 1 ,
wherein each of the SiGe layers is formed of a Si 1-x Ge x (0<x<1).
3. A semiconductor device according to the claim 1 , further comprising a SiGe strain applying layer,
wherein the silicon substrate is formed on the SiGe strain applying layer.
4. A semiconductor device according to the claim 3 ,
wherein the SiGe strain applying layer is formed of a Si 1-x Ge x (0<x<1).
5. A semiconductor device according to the claim 1 ,
wherein the first source region and the first drain region are formed of p-type impurity doped regions, and
wherein the second source region and the second drain region are formed of n-type impurity doped regions.
6. A semiconductor device according to the claim 1 ,
wherein the first source region and the second drain region are formed in the silicon substrate.
7. A semiconductor device according to the claim 1 ,
wherein each SiGe layers is formed by selectively grown in groove of the silicon substrate.
8. A semiconductor device, comprising:
a silicon substrate; and
a p-type MISFET having source region, a drain regions and a channel region which is arranged between the source region and the drain region,
wherein the silicon substrate is selectively etched,
wherein at least one said selectively etched portion is filled with an SiGe layer, and
wherein the drain region of the p-type MISFET is formed in the SiGe layers,
wherein a silicon film is formed on a top surface of the SiGe layer,
wherein the channel region is formed in the silicon substrate and is disposed on a sidewall of the SiGe layer, and
wherein a compressive stress is applied to the channel region in order to increase a drain current of the p-type MISFET.
9. A semiconductor device according to the claim 8 ,
wherein each said SiGe layer is formed of a Si 1-x Ge x (0<x<1).
10. A semiconductor device according to the claim 8 , further comprising a SiGe strain applying layer,
wherein the silicon substrate is formed on the SiGe strain applying layer.
11. A semiconductor device according to the claim 10 ,
wherein the SiGe strain applying layer is formed of a Si 1-x Ge x (0<x<1).
12. A semiconductor device according to the claim 8 ,
wherein the source and drain regions of the p-type MISFET are formed of p-type impurity doped regions.
13. A semiconductor device according to the claim 8
wherein the source region of the p-type MISFET is formed in the silicon substrate.
14. A semiconductor device according to the claim 8 ,
wherein each said SiGe layer is formed by selectively grown in groove of the silicon substrate.
15. A semiconductor device, comprising:
a silicon substrate; and
an n-type MISFET having a source region, a drain region and a channel region which is arranged between the source region and the drain region,
wherein the silicon substrate is selectively etched,
wherein at least one said selectively etched portion is filled with an SiGe layer, and
wherein the source region of the n-type MISFET is formed in the SiGe layers,
wherein a silicon film is formed on a top surface of the SiGe layer,
wherein the channel region is formed in the silicon substrate and is disposed on a sidewall of the SiGe layer, and
wherein a tensile stress is applied to the channel region in order to increase a drain current of the n-type MISFET
16. A semiconductor device according to the claim 15 ,
wherein each said SiGe layer is formed of a Si 1-x Ge x (0<x<1).
17. A semiconductor device according to the claim 15 , further comprising a SiGe strain applying layer,
wherein the silicon substrate is formed on the SiGe strain applying layer.
18. A semiconductor device according to the claim 17 ,
wherein the SiGe strain applying layer is formed of a Si 1-x Ge x (0<x<1).
19. A semiconductor device according to the claim 15 ,
wherein the source and drain regions of the n-type MISFET are formed of n-type impurity doped regions.
20. A semiconductor device according to the claim 15 ,
wherein the drain region of the n-type MISFET is formed in the silicon substrate.
21. A semiconductor device according to the claim 15 ,
wherein each said SiGe layer is formed by being selectively grown in groove of the silicon substrate.