Virtual memory mapping for efficient memory usage
View Patent ↗A processor (e.g. utilizing an operating system and/or circuitry) may access physical memory by paging, where a page is the smallest partition of memory mapped by the processor from a virtual address to a physical address. An application program executing on the processor addresses a virtual address space so that the application program may be unaware of physical memory paging mechanisms. A memory control layer manages physical memory space in units of sub-blocks, wherein a sub-blocks is smaller than a size of the page. Multiple virtual address blocks may be mapped to the same physical page in memory. A sub-block can be moved from a page (e.g. from one physical memory to a second physical memory) without moving other sub-blocks within the page in a manner that is transparent to the application program.
1. A system comprising:
a processing component configured to:
map a first virtual address associated with first data to a first page of physical memory, the first page having a predetermined page size corresponding to the smallest partition of memory mappable by the processing component from virtual addresses to physical addresses; and
allocate, based on a size of the first data, a first sub-block of physical memory resident in the first page for storing the first data, the first sub-block having a size smaller than the predetermined page size.
2. The system of claim 1 wherein the processing component is further configured to:
map a second virtual address associated with second data to the first page of physical memory; and
allocate, based on a size of the second data, a second sub-block resident in the first page for storing the second data.
3. The system of claim 2 wherein the processing component is further configured to move the first sub-block from a first physical memory to a second physical memory without moving the second sub-block from the first physical memory.
4. The system of claim 3 wherein the first physical memory comprises expensive storage and the second physical memory comprises inexpensive storage.
5. The system of claim 2 wherein the size of the first sub-block and the size of the second sub-block are the same.
6. The system of claim 2 wherein the size of the first sub-block and the size of the second sub-block are different.
7. The system of claim 1 wherein the first sub-block is selected from a set of sub-blocks having sub-blocks of different sizes.
8. The system of claim 1 wherein the system is a network switch.
9. The system of claim 8 wherein the first sub-block is allocated based upon a size of a received data packet.
10. A system comprising:
a processing component configured to:
map a first virtual address associated with first data to a first page of physical memory, the first page having a predetermined page size corresponding to the smallest partition of memory mappable by the processing component from virtual addresses to physical addresses; and
allocate a first sub-block of physical memory resident in the first page for storing the first data, wherein the first sub-block is selected from a set of sub-blocks having sub-blocks of at least two different sizes, and wherein the first sub-block has a size smaller than the predetermined page size.
11. The system of claim 10 wherein the processing component is further configured to:
map a second virtual address associated with second data to the first page of physical memory; and
allocate a second sub-block resident in the first page for storing the second data.
12. The system of claim 11 wherein the processing component is further configured to move the first sub-block from a first physical memory to a second physical memory without moving the second sub-block from the first physical memory.
13. The system of claim 11 wherein a size of the first sub-block is the same as a size of the second sub-block.
14. The system of claim 11 wherein a size of the first sub-block is different from a size of the second sub-block.
15. The system of claim 10 wherein the system is a network switch.
16. The system of claim 15 wherein the first sub-block is allocated based upon a size of a received data packet.
17. A system comprising:
a processing component configured to:
map a first virtual address associated with first data to a first page of physical memory; and
allocate a first sub-block of physical memory resident in the first page for storing the first data;
map a second virtual address associated with second data to the first page; and
allocate a second sub-block of physical memory resident in the first page for storing the second data,
wherein the first and second sub-blocks have sizes smaller than a predetermined page size, and
wherein the size of the first sub-block and the size of the second sub-block are different.
18. The system of claim 17 wherein the processing component is further configured to move the first sub-block from a first physical memory to a second physical memory without moving the second sub-block from the first physical memory.
19. The system of claim 17 wherein the system is a network switch.
20. The system of claim 19 wherein the first sub-block and second sub-blocks are allocated based upon sizes of received data packets.