Method and system of automatically correcting a sampling clock in a digital video system
View Patent ↗A method and system of automatically correcting a sampling clock in a digital video system are disclosed. Sampling clocks with different phases are generated and subjected in turn to analog-to-digital conversion (ADC). A difference of at least a pair of neighboring data out of the ADC with respect to each phase is determined. A maximum difference is determined, and the sampling clock with the phase corresponding to the maximum difference is thus generated.
1. A method of automatically correcting a sampling clock in a digital video system, the method comprising:
generating the sampling clock, which is used to trigger analog-to-digital conversion (ADC);
generating a plurality of sampling clocks with different phases in turn;
determining a difference of at least a pair of neighboring data from the ADC with respect to each of the phases;
determining a maximum one of the differences; and
generating the sampling clock with the phase corresponding to the maximum difference;
wherein the generating of the sampling clock comprises:
measuring scan line interval according to a synchronization signal and a system clock; and
finding at least one frequency for the sampling clock according to the measured scan line interval.
2. The method of claim 1 , wherein the digital video system is a digital display.
3. The method of claim 1 , wherein the synchronization signal is a horizontal synchronization signal.
4. The method of claim 1 , wherein one expectant frequency is found for the sampling clock.
5. The method of claim 4 , wherein sum of absolute differences between the neighboring data in at least a partial scan line is calculated with respect to each of the phases.
6. The method of claim 1 , wherein a plurality of candidate frequencies are found for the sampling clock.
7. The method of claim 6 , wherein the differences are determined further with respect to each of the candidate frequencies.
8. The method of claim 7 , wherein the sampling clock is generated further with the frequency corresponding to the maximum difference.
9. The method of claim 6 , wherein sum of absolute differences between the neighboring data in at least a partial scan line is calculated with respect to each of the phases and each of the candidate frequencies.
10. A system for automatically correcting a sampling clock in a digital video system, the system comprising:
an analog-to-digital converter (ADC) for converting an analog video signal into a digital video signal;
a clock generator for generating the sampling clock according to a synchronization signal and a system clock, wherein a plurality of sampling clocks with different phases are generated in turn and forwarded to the ADC;
a difference unit for determining a difference of at least a pair of neighboring data out of the ADC with respect to each of the phases; and
a controller for determining a maximum one of the differences and then controlling the clock generator to generate the sampling clock with the phase corresponding to the maximum difference;
wherein the clock generator comprises:
an interval measuring unit for measuring scan line interval according to the synchronization signal and the system clock; and
a lookup table for mapping the measured scan line interval to find at least one frequency for the sampling clock according to the measured scan line interval.
11. The system of claim 10 , wherein the digital video system is a digital display.
12. The system of claim 10 , wherein the synchronization signal is a horizontal synchronization signal.
13. The system of claim 10 , wherein one expectant frequency is found for the sampling clock.
14. The system of claim 13 , wherein the difference unit is a sum of absolute difference (SAD) unit, which calculates sum of absolute differences between the neighboring data in at least a partial scan line with respect to each of the phases.
15. The system of claim 10 , wherein a plurality of candidate frequencies are found for the sampling clock.
16. The system of claim 15 , wherein the differences are determined further with respect to each of the candidate frequencies.
17. The system of claim 16 , wherein the controller further issues a frequency control signal to control the clock generator.
18. The system of claim 17 , wherein the sampling clock is generated further with the frequency corresponding to the maximum difference.
19. The system of claim 15 , wherein the difference unit is a sum of absolute difference (SAD) unit, which calculates sum of absolute differences between the neighboring data in at least a partial scan line with respect to each of the phases and each of the candidate frequencies.
20. The system of claim 10 , further comprising a phase controller for controlling shift amount of phase by providing phase information to the clock generator according to a phase control signal issued by the controller.