IP Library Granted Patent US 8,339,534
Granted Patent B2
US 8,339,534 · App. 12/510,709 · Granted Dec 25, 2012

Display device

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Quick Facts
Patent No.
US 8,339,534
App. No.
12/510,709
Granted
Dec 25, 2012
Kind
B2
Abstract

A display device includes gate lines; data lines; charge control lines each including a charge control voltage input pad; first and second thin film transistors (TFTs) each including control and input electrodes connected to the gate and data lines, respectively; a first liquid crystal capacitor connected to an output electrode of the first TFT; a second liquid crystal capacitor connected to an output electrode of the second TFT; a charge control TFT including a control electrode and an input electrode connected to one of the charge control lines and the second pixel electrode, respectively; and a charge-down capacitor connected to an output electrode of the charge control TFT. A duration time of a turn-on voltage pulse applied to the charge control TFT is different from a duration time of a turn-on voltage pulse applied to the first TFT transistor or the second TFT.

Claims (86)

1. A display device, comprising:

gate lines extending along a first direction;

data lines extending along a second direction and intersecting the gate lines;

charge control lines extending along the first direction and each including a charge control voltage input pad disposed at an end thereof;

a first thin film transistor and a second thin film transistor each including a control electrode and an input electrode connected to one of the gate lines and one of the data lines, respectively;

a first liquid crystal capacitor connected to an output electrode of the first thin film transistor;

a second liquid crystal capacitor connected to an output electrode of the second thin film transistor;

wherein a charge control thin film transistor including a control electrode and an input electrode connected to one of the charge control lines and the second liquid crystal capacitor respectively; and

a charge-down capacitor connected to an output electrode of the charge control thin film transistor,

wherein a duration time of a turn-on voltage pulse applied to the charge control thin film transistor is different from a duration time of a turn-on voltage pulse applied to at least one of the first thin film transistor and the second thin film transistor.

2. The display device of claim 1 , wherein

the duration time of the turn-on voltage pulse applied to the charge control thin film transistor is less than the duration time of the turn-on voltage pulse applied to the at least one of the first thin film transistor and the second thin film transistor.

3. The display device of claim 2 , further comprising

pixels arranged in a matrix including pixel rows,

wherein the pixels include the first liquid crystal capacitor, the second liquid crystal capacitor, the charge-down capacitor, the first thin film transistor, the second thin film transistor and the charge control thin film transistor,

the data lines include a first data line and a second data line,

the gate lines include a first gate line connected to the pixels of an odd-numbered pixel row and a second gate line connected to the pixels of an even-numbered pixel row, and

the first gate line and the second gate line are supplied with a same gate voltage.

4. The display device of claim 3 , wherein

the pixels of the odd-numbered pixel row are connected to one data line of the first data line and the second data line, and

the pixels of the even-numbered unit pixel row are connected to another data line of the first data line and the second data line not connected to the pixels of the odd-numbered pixel row.

5. The display device of claim 4 , wherein

the charge control lines include a first charge control line connected to the pixels of the odd-numbered pixel row and a second charge control line connected to the pixels of the even-numbered pixel row, and

the first charge control line and the second charge control line are supplied with a same charge control turn-on voltage.

6. The display device of claim 5 , further comprising

a storage electrode line extending along the first direction,

wherein the storage electrode line includes a protrusion overlapping at least a portion of a charge control electrode of the charge down capacitor.

7. The display device of claim 1 , further comprising

a signal controller which applies a first clock signal for generating the turn-on voltage pulse applied to the charge control thin film transistor,

wherein the first clock signal is different from a second clock signal for generating the turn-on voltage pulse applied to the first thin film transistor and the second thin film transistor.

8. A display device comprising:

gate lines extending along a first direction;

data lines extending along a second direction and intersecting the gate lines;

charge control lines extending along the first direction and each including a charge control voltage input pad disposed at an end thereof;

a first thin film transistor and a second thin film transistor each including a control electrode and an input electrode connected to one of the gate lines and one of the data lines, respectively;

a first liquid crystal capacitor connected to an output electrode of the first thin film transistor;

a second liquid crystal capacitor connected to an output electrode of the second thin film transistor;

wherein a charge control this film transistor including a control electrode and an input electrode connected to one of the charge control lines and the second liquid crystal capacitor respectively; and

a charge-down capacitor connected to an output electrode of the charge control thin film transistor,

wherein a magnitude of a turn-on voltage applied to the charge control thin film transistor is different from a magnitude of a turn-on voltage applied to at least one of the first thin film transistor and the second thin film transistor.

9. The display device of claim 8 , wherein

the magnitude of the turn-on voltage applied to the charge control thin film transistor is less than the magnitude of the turn-on voltage applied to the at least one of the first thin film transistor and the second thin film transistor.

10. The display device of claim 9 , further comprising

pixels arranged in a matrix including pixel rows,

wherein the pixels include the first liquid crystal capacitor, the second liquid crystal capacitor, the charge-down capacitor, the first thin film transistor, the second thin film transistor and the charge control thin film transistor,

the data lines include a first data line and a second data line,

the gate lines include a first gate line connected to the pixels of an odd-numbered pixel row and a second gate line connected to the pixels of an even-numbered pixel row, and

the first gate line and the second gate line are supplied with a same gate voltage.

11. The display device of claim 10 , wherein

the pixels of the odd-numbered pixel row are connected to one data line of the first data line and the second data line, and

the pixels of the even-numbered unit pixel row are connected to another data line of the first data line and the second data line not connected to the pixels of the odd-numbered pixel row.

12. The display device of claim 11 , wherein

the charge control lines include a first charge control line connected to the pixels of the odd-numbered pixel row and a second charge control line connected to the pixels of the even-numbered pixel row, and

the first charge control line and the second charge control line are applied with a same charge control turn-on voltage.

13. The display device of claim 12 , further comprising

a storage electrode line extending along the first direction,

wherein the storage electrode line includes a protrusion overlapping at least a portion of a charge control electrode of the charge down capacitor.

14. The display device of claim 8 , wherein

the turn-on voltage applied to the charge control thin film transistor is generated by dividing the turn-on voltage applied to the at least one of the first thin film transistor and the second thin film transistor.

15. A display device comprising:

gate lines extending along a first direction;

data lines extending along a second direction and intersecting the gate lines;

charge control lines extending along the first direction and each including a charge control voltage input pad disposed at an end thereof;

a first thin film transistor and a second thin film transistor each including a control electrode and an input electrode connected to one of the gate lines and one of the data lines, respectively;

a first liquid crystal capacitor connected to an output electrode of the first thin film transistor;

a second liquid crystal capacitor connected to an output electrode of the second thin film transistor;

a charge control thin film transistor including a control electrode and an input electrode connected to one of the charge control lines and the second liquid crystal capacitor respectively; and

a charge-down capacitor connected to an output electrode of the charge control thin film transistor,

wherein a thickness of an insulating layer disposed between the control electrode and a semiconductor of the charge control thin film transistor is different from a thickness of an insulating layer disposed between the control electrode and a semiconductor of at least one of the first thin film transistor and the second thin film transistor.

16. The display device of claim 15 , wherein

the thickness of the insulating layer disposed between the control electrode and the semiconductor of the charge control thin film transistor is greater than the thickness of the insulating layer between the control electrode and the semiconductor of the first thin film transistor and the second thin film transistor by a value greater than or equal to about 1000 angstroms.

17. The display device of claim 16 , further comprising

pixels arranged in a matrix including pixel rows,

wherein the pixels include the first liquid crystal capacitor, the second liquid crystal capacitor, the charge-down capacitor, the first thin film transistor, the second thin film transistor and the charge control thin film transistor,

the data lines include a first data line and a second data line,

the gate lines include a first gate line connected to the pixels of an odd-numbered pixel row and a second gate line connected to the pixels of an even-numbered pixel row, and

the first gate line and the second gate line are supplied with a same gate voltage.

18. The display device of claim 17 , wherein

the pixels of the odd-numbered pixel row are connected to one data line of the first data line and the second data line, and

the pixels of the even-numbered unit pixel row are connected to another data line of the first data line and the second data line not connected to the pixels of the odd-numbered pixel row.

19. The display device of claim 18 , wherein

the charge control lines include a first charge control line connected to the pixels of the odd-numbered pixel row and a second charge control line connected to the pixels of the even-numbered pixel row, and

the first charge control line and the second charge control line are supplied with a same charge control turn-on voltage.

20. The display device of claim 19 , further comprising

a storage electrode line extending along the first direction,

wherein the storage electrode line includes a protrusion overlapping at least a portion of a charge control electrode of the charge down capacitor.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2022
From: SAMSUNG DISPLAY CO., LTD.
To: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 060778/0432 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2012
From: SAMSUNG ELECTRONICS CO., LTD.
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 029151/0055 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ADD THE NINTH INVENTOR THAT WAS NOT INCLUDED ON THE PREVIOUS SUBMISSION PREVIOUSLY RECORDED ON REEL 023016 FRAME 0190. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 13, 2009
From: LEE, JUN-PYO; SON, SUN-KYU; SHIN, OK-KWON; KIM, JUNG-WON; CHOI, HEE-JIN; KIM, SANG-SOO; LEE, HYONG-RAE; KANG, DUK-HWAN; LEE, KWAN-WOO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 023097/0387 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2009
From: LEE, JUN-PYO; SON, SUN-KYU; SHIN, OK-KWON; KIM, JUNG-WON; CHOI, HEE-JIN; KIM, SANG-SOO; LEE, HYONG-RAE; KANG, DUK-HWAN
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 023016/0190 →