IP Library Granted Patent US 8,312,343
Granted Patent B2
US 8,312,343 · App. 12/510,859 · Granted Nov 13, 2012

Systems and methods for re-using decoding parity in a detector circuit

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Quick Facts
Patent No.
US 8,312,343
App. No.
12/510,859
Granted
Nov 13, 2012
Kind
B2
Abstract

Various approaches related to systems and methods for reusing decoding parity.

Claims (46)

1. A data processing system, the system comprising:

a data detection circuit, wherein the data detection circuit includes pruning one or more trellis data paths based upon satisfaction of a parity equation including active bits grouped from an LDPC codeword, and wherein the active bits include at least one LDPC parity bit;

an ungrouping circuit, wherein the ungrouping circuit is operable to create an LDPC format data set; and

a decoding circuit, wherein the decoding circuit performs an LDPC decoding algorithm on the LDPC format data set.

2. The system of claim 1 , wherein the data detection circuit performs a soft output Viterbi algorithm data detection.

3. The system of claim 1 , wherein the LDPC codeword is a transferred LDPC codeword, and wherein the system further comprises:

a grouping circuit, wherein the grouping circuit receives a pre-transfer LDPC codeword, and wherein the grouping circuit assembles the active bits corresponding to a parity check equation of the pre-transferred LDPC codeword to yield a grouped data set.

4. The system of claim 3 , wherein the system further comprises:

a transmission circuit, wherein the transmission circuit transmits the grouped data set.

5. A method for data processing, the method comprising:

receiving an LDPC codeword; and

grouping active bits from the LDPC codeword into a series of data bits including one or more user data bits including and at least one LDPC parity bit, and wherein the series of data bits satisfies an LDPC parity equation.

6. The method of claim 5 , wherein the method further comprises:

transferring the series of data bits;

determining whether to prune one or more trellis data paths based on satisfaction of a parity equation corresponding to the series of data bits; and

performing a data detection algorithm on the series of data bits using the trellis data paths.

7. The method of claim 6 , wherein the data detection algorithm is a soft output Viterbi algorithm.

8. The method of claim 6 , wherein determining whether to prune the one or more trellis data paths includes:

determining the number of errors remaining in the series of consecutive bits; and

wherein the data detection is performed without pruning the one or more trellis data paths when the number of errors remaining exceeds a threshold value.

9. The method of claim 6 , wherein determining whether to prune the one or more trellis data paths includes:

determining the number of prior detection/decoding iterations that have been performed; and

wherein the data detection is performed without pruning the one or more trellis data paths when the number of prior detection/decoding iterations are less than a threshold value.

10. The method of claim 6 , wherein determining whether to prune the one or more trellis data paths includes always determining to prune the one or more trellis data paths.

11. A method for data processing, the method comprising:

receiving a grouped data set, wherein the grouped data set includes active bits of an LDPC codeword grouped together into a series of consecutive bits including at least one LDPC parity bit, and wherein the series of consecutive bits when correct satisfy a parity equation; and

performing a data detection algorithm on the series of consecutive bits, wherein the detection algorithm includes pruning one or more trellis data paths based on satisfaction of a parity equation.

12. The method of claim 11 , wherein performing the data detection algorithm yields a detected output, and wherein the method further comprises:

ungrouping the detected output, wherein an LDPC format data set created using the detected output.

13. The method of claim 12 , wherein the method further comprises:

providing the LDPC format data set to an LDPC decoder;

decoding the LDPC format data set to yield a data output.

14. The method of claim 13 , wherein the series of consecutive bits is a first series of consecutive bits, and wherein the method further comprises:

determining that the data output failed to converge; and

re-grouping the data output to form the active bits of the LDPC format data set modified by the LDPC decoder into a second series of consecutive bits including at least one LDPC parity bit, and wherein the series of consecutive bits when correct satisfy the parity equation.

15. The method of claim 14 , performing the data detection algorithm on the second series of consecutive bits, wherein the detection algorithm includes pruning one or more trellis data paths based on satisfaction of the parity equation.

16. The method of claim 11 , wherein the method further comprises:

determining whether to prune the one or more trellis data paths, wherein the data detection is performed without pruning the one or more trellis data paths when it is determined not to prune the one or more trellis data paths.

17. The method of claim 16 , wherein determining whether to prune the one or more trellis data paths includes:

determining the number of errors remaining in the series of consecutive bits; and

wherein the data detection is performed without pruning the one or more trellis data paths when the number of errors remaining exceeds a threshold value.

18. The method of claim 17 , wherein the threshold value is programmable.

19. The method of claim 16 , wherein determining whether to prune the one or more trellis data paths includes:

determining the number of prior detection/decoding iterations that have been performed; and

wherein the data detection is performed without pruning the one or more trellis data paths when the number of prior detection/decoding iterations is less than a threshold value.

20. The method of claim 19 , wherein the threshold value is programmable.

Assignments (10)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2009
From: ZHONG, HAO; TAN, WEIJUN; HAN, YANG; LI, ZONGWANG; YANG, SHAOHUA; LEE, YUAN XING
To: LSI CORPORATION
Reel/Frame 023017/0341 →