HARDWARE TRANSACTIONAL MEMORY SUPPORT FOR PROTECTED AND UNPROTECTED SHARED-MEMORY ACCESSES IN A SPECULATIVE SECTION
A system and method is disclosed for implementing a hardware transactional memory system capable of executing a speculative section of code containing both protected and unprotected memory access operations. A processor in a multi-processor system is configured to execute a section of code that performs a transaction using shared memory, such that a first subset of memory operations in the section of code is performed atomically with respect to the concurrent execution of the one or more other processors and a second subset of memory operations in the section of code is not. In some embodiments, the section of code includes a plurality of declarator operations, each of which is executable to designate a respective location in the shared memory as protected.
1 . An apparatus, comprising:
a processor coupleable to one or more other processors, wherein the processor and the one or more other processors are coupleable to a shared memory and are configured to execute instructions concurrently;
wherein the processor is configured to execute a section of code that performs a transaction using the shared memory such that a first subset of memory operations in the section of code is performed atomically with respect to the concurrent execution of the one or more other processors and a second subset of memory operations in the section of code is not guaranteed to be performed atomically with respect to the concurrent execution of the one or more other processors, wherein each of the first subset of memory operations is executable to access at least one of the memory locations in the shared memory.
2 . The apparatus of claim 1 , wherein the section of code comprises a plurality of declarator operations, each of which is executable to designate a respective location in the shared memory as protected, wherein each of the memory operations in the first subset accesses at least one of the protected shared memory locations and wherein none of the second subset of memory operations accesses any of the protected shared memory locations.
3 . The apparatus of claim 2 , wherein the processor is further configured to detect an abort condition while executing the section of code, and in response thereto, abort the attempt to execute the section of code and reattempt to execute the section of code.
4 . The apparatus of claim 3 , wherein the processor is configured to detect the abort condition by detecting that another processor of the one or more other processors has executed an instruction accessing one of the memory locations designated as protected by one of the plurality of declarator operations.
5 . The apparatus of claim 3 , wherein the abort condition is caused by a hardware capacity limitation of the processor being exceeded.
6 . The apparatus of claim 3 , wherein the processor is configured to abort the attempt to execute the section of code by discarding any modifications made by the first subset of memory operations to one or more of the memory locations designated as protected by ones of the plurality of declarator operations.
7 . The apparatus of claim 6 , wherein the processor is configured to perform said discarding by restoring a respective original value to each of the modified one or more of the memory locations designated as protected, wherein a given respective original value is the value that each of the memory locations held before the section of code was executed.
8 . The apparatus of claim 6 , wherein the processor is configured to execute the section of code by delaying the execution of store operations of the first subset of memory operations in a store queue until the end of the section of code and wherein said discarding any modifications includes discarding the store operations from the store queue.
9 . The apparatus of claim 6 , wherein the processor is further configured to, after said discarding, continue to execute the section of code without executing any store operations of the first subset of memory operations.
10 . The apparatus of claim 3 , wherein the processor is configured to execute the section of code by recording a checkpoint at the start of the section of code, wherein said recording includes recording one or more respective values of one or more hardware registers, and wherein the processor is configured to reattempt the execution of the section of code by restoring the recorded one or more values to their respective hardware registers.
11 . The apparatus of claim 2 , wherein the section of code further comprises a release instruction specifying one or more of the memory locations designated as protected, wherein in response to the processor executing the release instruction, the specified one or more memory locations are no longer designated as protected.
12 . A computer-implemented method comprising:
a first processor of a plurality of processors commencing execution of a section of code that performs a shared memory transaction, wherein the plurality of processors are coupled to a shared memory and are configured to execute program instructions concurrently, wherein the section of code comprises:
a plurality of declarator operations, each of which is executable to designate a respective location in the shared memory as protected;
a plurality of memory access operations accessing locations in the shared memory, wherein each of a first subset of the plurality of memory access operations is executable to access at least one of the memory locations designated as protected by one of the plurality of declarator operations, and wherein none of a second subset of the plurality of memory access operations are executable to access any of the memory locations designated as protected by the plurality of declarator operations; and
the first processor executing the section of code such that the first subset of memory operations is performed atomically with respect to the concurrent execution of the plurality of processors and the second subset of memory operations is not performed atomically with respect to the concurrent execution of the plurality of processors.
13 . The computer-implemented method of claim 12 , wherein executing the section of code further comprises the first processor detecting an abort condition, and in response thereto, the first processor aborting the attempt to execute the section of code and reattempting to execute the section of code.
14 . The computer-implemented method of claim 13 , wherein the detecting includes determining that another processor of the plurality of processors has executed an instruction accessing one of the memory locations designated as protected by one of the plurality of declarator operations.
15 . The computer-implemented method of claim 13 , wherein said aborting the attempt comprises discarding modifications made by execution of ones of the first subset of the plurality of memory operations to one or more of the memory locations designated as protected.
16 . The computer-implemented method of claim 13 , wherein in response to said aborting, executing a remaining portion of the section of code such that no store operations of the first subset of memory operations in the remaining portion of the section is performed.
17 . The computer-implemented method of claim 12 , wherein the section of code further comprises a release instruction specifying one or more of the memory locations designated as protected, and wherein in response to the first processor executing the release instruction, the memory location is no longer designated as protected.
18 . An article of manufacture comprising a computer-readable storage medium having stored thereon program instructions that, if executed by a first of a plurality of processors that are coupled to a shared memory and that are configured to execute instructions concurrently, cause the first processor to perform a method comprising:
executing a section of code that performs a shared memory transaction using the shared memory such that a first plurality of memory access operations in the section of code that access locations in the shared memory is performed atomically with respect to the concurrent execution of the plurality of processors and a second plurality of memory access operations in the section of code that access locations in the shared memory is not guaranteed to be performed atomically with respect to the concurrent execution of the plurality of processors.
19 . The article of manufacture of claim 18 , wherein each of the first plurality of memory access operations is executable by the first processor to access at least one location in the shared memory designated as protected, and wherein none of the memory access operations in the second plurality of memory access operations are executable to access a memory location in the shared memory that is designated as protected.
20 . The article of manufacture of claim 19 , wherein the executing includes detecting an indication of an abort condition while executing the section of code, and in response thereto, aborting the attempt to execute the section of code and reattempting to execute the section of code;
wherein the indication is indicative of 1) a second processor of the plurality of processors having executed an instruction accessing one of the memory locations in the shared memory designated as protected; or 2) a hardware capacity limitation of the first processor having been exceeded.