Systems and methods for utilizing circulant parity in a data processing system

1. A method for data processing, the method comprising:

receiving a codeword, wherein the codeword includes at least a first circulant having a plurality of data bits and a first circulant parity bit, a second circulant having a plurality of data bits and a second circulant parity bit, and one or more codeword parity bits;

decoding the codeword using the one or more codeword parity bits to access the first circulant and the second circulant, wherein decoding the codeword results in a satisfaction of one or more codeword parity check equations relying on the codeword parity bits;

performing a first circulant parity check on the first circulant, wherein the first circulant parity check fails;

performing a second circulant parity check on the second circulant; and

based at least in part on the failure of the first circulant parity check, modifying soft data derived from the decoding to indicate that the first circulant is likely incorrect.

2. The method of claim 1 , wherein the decoding is low density parity check decoding.

3. The method of claim 1 , wherein the method further comprises:

receiving a data input;

assembling data packets of a circulant size less parity bits;

calculating parity for each of the data packets;

augmenting each of the data packets with the calculated parity to create circulants that together form a completed data set; and

encoding the completed data set to yield the codeword.

4. The method of claim 3 , wherein the encoding is low density parity check encoding.

5. The method of claim 1 , wherein the codeword is derived from a magnetic storage medium.

6. The method of claim 1 , wherein the codeword is derived from a wireless transfer medium.

7. The method of claim 1 , wherein the method further comprises:

decoding the codeword using the one or more codeword parity bits and the modified soft data to access the first circulant and the second circulant.

8. The method of claim 7 , wherein the method further comprises:

performing another first circulant parity check on the first circulant; and

performing another second circulant parity check on the second circulant.

9. The method of claim 1 , wherein decoding the codeword results in a satisfaction of all codeword parity check equations relying on the codeword parity bits, wherein the first circulant parity check succeeds, wherein the second circulant parity check succeeds, and wherein the method further comprises:

stripping the first circulant parity from the first circulant to yield a first user data set;

stripping the second circulant parity from the second circulant to yield a second user data set; and

providing at least the first user data set and the second user data set as a data output.

10. The method of claim 1 , wherein decoding the codeword results in the failure of one or more parity check equations, wherein the first circulant parity check fails, and wherein the method further comprises:

modifying soft data derived from the decoding to indicate that the first circulant is likely incorrect; and

decoding the codeword using the one or more codeword parity bits and the modified soft data.

11. The method of claim 1 , wherein decoding the codeword results in the failure of one or more parity check equations, wherein the first circulant parity check fails, wherein the second circulant parity check succeeds, and wherein the method further comprises:

identifying a unique bit within the first circulant that is used in one of the one or more failed parity check equations; and

flipping the unique bit.

12. The method of claim 11 , wherein the method further comprises:

stripping the first circulant parity from the first circulant to yield a first user data set;

stripping the second circulant parity from the second circulant to yield a second user data set; and

providing at least the first user data set and the second user data set as a data output.

13. A data decoder circuit, the circuit comprising:

a low density parity check decoder, wherein the low density parity check decoder is operable to:

receive a codeword including at least a first circulant, a second circulant, and one or more codeword parity bits, wherein the first circulant includes a plurality of data bits and a first circulant parity bit, and wherein the second circulant includes a plurality of data bits and a second circulant parity bit; and

decode the codeword using the codeword parity bits to yield the first circulant and the second circulant; and

a circulant parity check circuit operable to:

determine whether the parity of the first circulant is correct, wherein the first circulant parity check fails;

determine whether the parity of the second circulant is correct; and

based at least in part on the failure of the first circulant parity check, modifying soft data derived from the decoding to indicate that the first circulant is likely incorrect.

14. The circuit of claim 13 , wherein the circuit is operable to provide a data output when at least the low density parity check decoder converges and both the parity of the first circulant and the parity of the second circulant are correct.

15. A data processing system, the data processing system comprising:

a data decoder circuit operable to:

receive a codeword including: a first subset having a first data set and at least a first parity bit, a second subset having a second data set and at least a second parity bit, and one or more codeword parity bits;

apply a data decoding algorithm to the codeword using the codeword parity bits to yield a decoded output, wherein the decoded output includes the first subset and the second subset; and

a subset parity check circuit operable to:

perform a first parity check on the first subset using the first parity bit to yield a first parity result, wherein the first parity result indicates a failure of the first parity check; and

perform a second parity check on the second subset using the second parity bit to yield a second parity result; and

based at least in part on the first parity result, modifying soft data of the decoded output corresponding to the first subset to indicate that that the first subset is likely incorrect.

16. The data processing system of claim 15 , wherein the data decoder is operable to indicate a problem condition when the application of the data decoding algorithm converged and failure of first parity check.

17. The data processing system of claim 15 , wherein the data processing system is implemented as part of an integrated circuit.

18. The data processing system of claim 15 , wherein the data processing system is implemented as part of a data transfer system.

19. The data processing system of claim 18 , wherein the data transfer system is a wireless transfer medium.

20. The data processing system of claim 18 , wherein the data transfer system is a storage device.

21. The data processing system of claim 20 , wherein the data processing system is incorporated in a read channel circuit, and wherein the storage device further comprises:

a storage medium; and

a read/write head assembly disposed in relation to the storage medium and operable to access a representation of the codeword from the storage medium.

22. The data processing system of claim 21 , wherein the read/write head assembly is further operable to write the representation of the codeword to the storage medium, and wherein the read channel circuit further comprises:

a parity augmentation circuit, wherein the parity augmentation circuit is operable to:

receive an input data signal;

break the input data signal into a first data set and a second data set;

calculate the first parity bit based on the first data set;

augment the first data set with the first parity bit to yield a first subset;

calculate the second parity bit based on the second data set;

augment the second data set with the second parity bit to yield a second subset; and

an encoding circuit operable to perform low density parity check encoding on a combination of the first subset and the second subset to yield the codeword.

23. The data processing system of claim 15 , wherein the data decoding algorithm is a low density parity check decoding algorithm.

24. The data processing system of claim 15 , wherein the decoded output it a first decoded output, and wherein the data decoder circuit is further operable to re-apply the data decoding algorithm to the codeword guided by the first decoded output including the modified soft data to yield a second decoded output.