IP Library Granted Patent US 8,577,024
Granted Patent B2
US 8,577,024 · App. 12/511,042 · Granted Nov 5, 2013

Concealing plain text in scrambled blocks

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Quick Facts
Patent No.
US 8,577,024
App. No.
12/511,042
Granted
Nov 5, 2013
Kind
B2
Abstract

An apparatus generally having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) divide a plain text into at least three input blocks and (ii) generate at least three scrambled blocks by scrambling the input blocks using a first cipher process. The first cipher process may be configured such that a first of the input blocks does not affect the generation of a last scrambled block. The second circuit may be configured to (i) generate at least three output blocks by de-scrambling the scrambled blocks using a second cipher process and (ii) reconstruct the plain text from the output blocks. The second cipher process may be configured such that a first of the scrambled blocks affects the generation of all of the output blocks.

Claims (36)

1. An apparatus comprising:

a first circuit configured to (i) divide a plain text into at least three input blocks and (ii) generate at least three scrambled blocks by scrambling said input blocks using a first cipher process, said first cipher process being configured such that a first of said input blocks does not affect said generation of a last of said scrambled blocks; and

a second circuit configured to (i) generate at least three output blocks by de-scrambling said scrambled blocks using a second cipher process and (ii) reconstruct said plain text from said output blocks, said second cipher process being configured such that the plain text from a first of said scrambled blocks is arithmetically combined with at least one other of said output blocks in de-scrambling the at least one other of said output blocks.

2. The apparatus according to claim 1 , wherein said second circuit is further configured to authenticate a message within said plain text using an authentication code within said plain text.

3. The apparatus according to claim 1 , wherein said first circuit is further configured to (i) generate a data field incorporating an authentication code and (ii) generate a signature based on both said data field and a private key.

4. The apparatus according to claim 1 , wherein said second circuit is further configured to store said scrambled blocks such as to be inaccessible outside of said second circuit.

5. The apparatus according to claim 1 , wherein said first circuit is further configured to obfuscate said scrambled blocks before said scrambled blocks are transferred to said second circuit.

6. The apparatus according to claim 1 , wherein (i) said first cipher process comprises an Advanced Encryption Standard-Cipher Block Chaining decryption process and (ii) said second cipher process comprises an Advanced Encryption Standard-Cipher Block Chaining encryption process.

7. The apparatus according to claim 2 , wherein said second circuit is further configured to generate said output blocks such that said message is both (i) recovered and (ii) authenticated in a single pass through said second circuit using a single buffer.

8. The apparatus according to claim 3 , wherein said second circuit is further configured to (i) reconstruct said data field using a public key that corresponds to said private key, (ii) validate said scrambled blocks using said authentication code and (iii) authenticate a message within said plain text using said authentication code.

9. The apparatus according to claim 4 , wherein said second circuit is further configured to (i) access said scrambled blocks during a secure boot and (ii) provision said second circuit using said plain text.

10. The apparatus according to claim 5 , wherein said second circuit is further configured to de-obfuscate said scrambled blocks prior to said de-scrambling.

11. A method for concealing plain text in scrambled blocks, comprising the steps of:

(A) dividing said plain text into at least three input blocks via a pre-processor;

(B) generating via a scrambler, at least three of said scrambled blocks by scrambling said input blocks using a first cipher process in a first circuit, said first cipher process being configured such that a first of said input blocks does not affect said generation of a last of said scrambled blocks;

(C) generating, via a descrambler, at least three output blocks by de-scrambling said scrambled blocks using a second cipher process in a second circuit, said second cipher process being configured such that the plain text from a first of said scrambled blocks is arithmetically combined with at least one other of said output blocks in de-scrambling the at least one other of said output blocks; and

(D) reconstructing said plain text from said output blocks via a post processor.

12. The method according to claim 11 , further comprising the step of:

authenticating a message within said plain text using an authentication code within said plain text.

13. The method according to claim 11 , further comprising the steps of:

generating a data field incorporating an authentication code; and

generating a signature based on both said data field and a private key.

14. The method according to claim 11 , further comprising the step of:

storing said scrambled blocks in said second circuit such as to be inaccessible outside of said second circuit.

15. The method according to claim 11 , further comprising the step of:

obfuscating said scrambled blocks before said scrambled blocks are transferred to said second circuit.

16. The method according to claim 12 , wherein said output blocks are generated such that said message is both (i) recovered and (ii) authenticated in a single pass through said second circuit using a single buffer.

17. The method according to claim 13 , further comprising the steps of:

reconstructing said data field using a public key that corresponds to said private key;

validating said scrambled blocks using said authentication code; and

authenticating a message within said plain text using said authentication code.

18. The method according to claim 14 , further comprising the steps of:

accessing said scrambled blocks during a secure boot of said second circuit; and

provisioning said second circuit using said plain text.

19. The method according to claim 15 , further comprising the step of:

de-obfuscating said scrambled blocks prior to said descrambling.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2025
From: PIXELWORKS, INC.
To: BITHARMONY, LLC
Reel/Frame 073147/0288 →
RELEASE OF SECURITY INTEREST Recorded Oct 21, 2025
From: COMERICA BANK
To: VIXS SYSTEMS, INC.
Reel/Frame 073158/0132 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2021
From: VIXS SYSTEMS, INC.
To: PIXELWORKS, INC.
Reel/Frame 056697/0568 →
SECURITY INTEREST Recorded Jul 18, 2016
From: VIXS SYSTEMS INC.
To: COMERICA BANK
Reel/Frame 039380/0479 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2009
From: DUCHARME, PAUL D.; JAO, WEIGUO
To: VIXS SYSTEMS, INC.
Reel/Frame 023026/0740 →